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Motorola
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Part No. |
MPC7457ED MPC7457EC
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OCR Text |
...per-block basis -- 64-byte, two-sectored line size -- Parity support on cache Level 3 (L3) cache interface (not implemented on MPC7447) -- Provides critical double-word forwarding to the requesting unit -- Internal L3 cache controller and t... |
Description |
RISC Microprocessor Hardware Specifications
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File Size |
965.05K /
60 Page |
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it Online |
Download Datasheet
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Motorola
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Part No. |
MPC7451ED MPC7451EC
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OCR Text |
...per-block basis -- 64-byte, two-sectored line size -- Parity support on cache * Level 3 (L3) cache interface -- Provides critical double-word forwarding to the requesting unit -- Internal L3 cache controller and tags -- External data SRAMs ... |
Description |
RISC Microprocessor Hardware Specifications
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File Size |
661.77K /
52 Page |
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it Online |
Download Datasheet
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Motorola
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Part No. |
MPC7450ED MPC7450EC
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OCR Text |
...per-block basis -- 64-byte, two-sectored line size -- Parity support on cache * Level 3 (L3) cache interface -- Provides critical double-word forwarding to the requesting unit -- Internal L3 cache controller and tags -- External data SRAMs ... |
Description |
RISC Microprocessor Hardware Specifications
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File Size |
310.76K /
52 Page |
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it Online |
Download Datasheet
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Atmel Corp.
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Part No. |
AT91F40816-33CI
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OCR Text |
...lt read and 2.7-volt byte-write sectored flash memory die in a single compact 120-ball bga device. the address, data and control signals, except the flash memory enable, are internally interconnected. the architecture consists of two main b... |
Description |
ARM Thumb Microcontrollers
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File Size |
144.92K /
22 Page |
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it Online |
Download Datasheet
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Price and Availability
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