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SGS Thomson Microelectronics
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| Part No. |
M27C256B-12XF1
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| OCR Text |
...t a =25 c, f = 1 mhz) note: 1. sampled only, not 100% tested. symbol parameter test condit ion min max unit c in input capacitance v in =0v...data is desired from a particular memory de- vice.
m27c256b 6/16 figure 5. read mode ac waveforms ... |
| Description |
256 Kbit (32Kb x 8) EPROM, 5V, 120ns
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| File Size |
107.18K /
16 Page |
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it Online |
Download Datasheet
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Cypress
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| Part No. |
CY7C1444AV33-1XWI
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| OCR Text |
... one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are ...data pins. oe is masked during the first clock of a read cycle when emerging fr om a deselected st... |
| Description |
36-Mbit (1 M 36) Pipelined DCD Sync SRAM
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| File Size |
448.49K /
24 Page |
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it Online |
Download Datasheet |
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White Electronic Designs
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| Part No. |
EDI9LC644V1312BC EDI9LC644V1310BC EDI9LC644V1512BC EDI9LC644V2010BC EDI9LC644V1612BC EDI9LC644V1510BC EDI9LC644V1610BC EDI9LC644V2012BC
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| OCR Text |
...ut. all of the ssram inputs are sampled on the rising edge of the clock. ssads when sampled at the positive rising edge of the clock, ssads,...data input/output are multiplexed on the same pins. output bwe 0-3 input pulse bwe 0-3 perform the ... |
| Description |
SSRAM access:133MHz; SDRAM access:125MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:133MHz; SDRAM access:100MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:150MHz; SDRAM access:125MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:200MHz; SDRAM access:100MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:166MHz; SDRAM access:125MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:150MHz; SDRAM access:100MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:166MHz; SDRAM access:100MHz; 128K x 32 SSRAM/1M x 32 SDRAM
SSRAM access:200MHz; SDRAM access:125MHz; 128K x 32 SSRAM/1M x 32 SDRAM
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| File Size |
1,544.49K /
25 Page |
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it Online |
Download Datasheet |
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MAXIM - Dallas Semiconductor
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| Part No. |
DS2143Q
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| OCR Text |
...ta. transmit nrz serial data, sampled on the falling edge of tclk. 3tchclko transmit channel clock. 256 khz clock which pulses high during the lsb of each channel. useful for parallel-to-serial conversion of channel data. see section ... |
| Description |
E1 Controller
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| File Size |
553.11K /
44 Page |
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it Online |
Download Datasheet |
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MAXIM - Dallas Semiconductor
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| Part No. |
DS2143QTR
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| OCR Text |
...ta. transmit nrz serial data, sampled on the falling edge of tclk. 3t c h c l ko transmit channel clock. 256 khz clock which pulses high during the lsb of each channel. useful for parallel-to-serial conversion of channel data. see sec... |
| Description |
E1 Controller
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| File Size |
598.06K /
44 Page |
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it Online |
Download Datasheet |
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Taiwan Memory Technolog...
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| Part No. |
T14L1024N-10W
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| OCR Text |
...pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v inpu...data valid to end of write t dw 6 - 8 - 8 - ns data hold from end of write t dh 0 - 0 - 0 - n... |
| Description |
128K X 8 HIGH SPEED CMOS STATIC RAM
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| File Size |
87.40K /
13 Page |
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it Online |
Download Datasheet |
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Taiwan Memory Technolog...
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| Part No. |
T14L1024A
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| OCR Text |
...pf note: these parameters are sampled but not 100% tested. ac test conditions parameter conditions input pulse levels 0v to 3v inpu...data valid to end of write t dw 6 - 8 - 8 - ns data hold from end of write t dh 0 - 0 - 0 - n... |
| Description |
128K X 8 HIGH SPEED CMOS STATIC RAM
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| File Size |
85.93K /
12 Page |
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it Online |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16SM AS4C32M16SM-7TIN
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| OCR Text |
...put data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high - z state (two - clock latency)...data input/output: data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are nc for x8; and ... |
| Description |
PC133-compliant
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| File Size |
2,741.77K /
73 Page |
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it Online |
Download Datasheet |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16MD1A AS4C32M16MD1A-5BCN
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| OCR Text |
... and control input signals are sampled on the cr ossing of the positive edge of ck and negative edge of ck. input and output data is referenced to the crossing of ck and ck (both direct ions of crossing). internal clock signals are der... |
| Description |
60 ball FBGA PACKAGE
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| File Size |
2,393.14K /
53 Page |
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it Online |
Download Datasheet |
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Alliance Semiconductor ...
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| Part No. |
AS4C32M16D2A-25BCN
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| OCR Text |
...k. all sdram input signals are sampled on the crossing of positive edge of ck and negative edge of ck#. output (read) data is referenced to the crossings of ck and ck# (both directions of crossing). cke input clock enable: cke ac... |
| Description |
Fully synchronous operation
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| File Size |
2,185.60K /
61 Page |
View
it Online |
Download Datasheet |
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