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low-jitter Datasheet PDF File

For low-jitter Found Datasheets File :: 23760 Search Time::2.203ms
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				ZARLINK SEMICONDUCTOR INC
Part No.	MT8941AP MT8941APR
OCR Text	...committed two-input nand gate ? low power cmos technology applications ? synchronization and timing control for t1 and cept digital...jitter performance over the mt8940. the two devices also have some functional differences, which a...
Description	SPECIALTY TELECOM CIRCUIT, PQCC28
File Size	556.90K / 24 Page	View it Online	Download Datasheet

				IDT
Part No.	ICS889872
OCR Text	...t and enable/disable pin. w hen low, resets the divider select, and align bank a and bank b edges. in addition, when low, bank a and bank...jitter on the input will equal the jitter on the output. the part does not add jitter. symbol param...
Description	DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
File Size	1,045.91K / 14 Page	View it Online	Download Datasheet

				Analog Devices
Part No.	AD9525/PCBZ-VCO AD9525BCPZ-REEL7
OCR Text	low jitter clock generator with eight lvpecl outputs data sheet ad9525 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is a ssumed by an...
Description	Low Jitter Clock Generator with Eight LVPECL Outputs Low Jitter Clock Generator with Eight LVPECL Outputs
File Size	719.10K / 48 Page	View it Online	Download Datasheet

				PhaseLink
Part No.	PLL205-16
OCR Text	...d interval. it will generate a low reset output when timer expired. spread spectrum 0.25% center, 0.5% center, 0.75% center, and 0 to - 0.5% downspread. 50% duty cycle with low jitter. available in 300 mil 48 pin sso...
Description	Programmable Clock Generator
File Size	272.38K / 16 Page	View it Online	Download Datasheet

				PhaseLink
Part No.	PLL205-14
OCR Text	...nd interval. it will generate a low reset output when timer expired. spread spectrum 0.25% center, 0.5% center, 0.75% center, and 0 to -0.5% downspread. 50% duty cycle with low jitter. available in 300 mil 48 pin ssop. block ...
Description	Programmable Clock Generator
File Size	288.85K / 13 Page	View it Online	Download Datasheet

				PhaseLink
Part No.	PLL205-04
OCR Text	...nspread. 50% duty cycle with low jitter. available in 300 mil 48 pin ssop. block diagram pin configuration note: ^: pull up v: pull down #: active low * : bi-directional up latched at power-up power group vdd1: ref(0:1),...
Description	Programmable Clock Generator
File Size	262.37K / 12 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB7L11M
OCR Text	...output structure, optimized for low skew and minimal jitter. the device is functionally equivalent to the ep11, lvep11, or sg11 devices. device produces two identical output copies of clock or data op erating up to 8 ghz or 12 gb/s, respect...
Description	2.5V/3.3V Differential 1:2 Clock/Data Fanout Buffer/Translator with CML Outputs and Internal Termination(带CML输出和内部端口的2.5V/3.3V差分1:2时钟/数据输出缓冲转换 2.5V/3.3V的差1:2时钟/数据扇出缓冲带CML输出和内部终止翻译（带白血病输出和内部端口.5V/3.3V的差1:2时钟/数据输出缓冲转换器）
File Size	212.18K / 11 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB3N511 NB3N511DG NB3N511DR2G
OCR Text	...echniques are used to produce a low jitter, ttl level clock output up to 200 mhz with a 50% duty cycle. an output enable (oe) pin is provided, and when asserted low, the clock output goes into tri ? state (high impedance). the nb3n511 is c...
Description	3.3V / 5.0V 14 MHz to 200 MHz PLL Clock Multiplier
File Size	104.29K / 6 Page	View it Online	Download Datasheet

				ON Semiconductor
Part No.	NB3N501DG NB3N501DR2G
OCR Text	...echniques are used to produce a low jitter, ttl level clock output up to 160 mhz with a 50% duty cycle. an output enable (oe) pin is provided, and when asserted low, the clock output goes into tri ? state (high impedance). the nb3n501 is c...
Description	3.3V / 5.0V 13 MHz to 160 MHz PLL Clock Multiplier
File Size	124.73K / 6 Page	View it Online	Download Datasheet

For low-jitter Found Datasheets File :: 23760 Search Time::2.203ms
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