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MOTOROLA[Motorola, Inc]
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| Part No. |
MPC859TTSD MPC859DSL MPC859P MPC859T MPC859TTS
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| OCR Text |
...ddress lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to ...way, set associative with physical addressing. It allows single-cycle access on hits with no added l... |
| Description |
PowerQUICC⑩ Family Technical Summary
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| File Size |
272.11K /
12 Page |
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it Online |
Download Datasheet
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Motorola
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| Part No. |
MPC755ED MPC755EC
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| OCR Text |
...structure -- 32K, 32-byte line, eight-way set-associative instruction cache (iL1) -- 32K, 32-byte line, eight-way set-associative data cache (dL1) -- Cache locking for both instruction and data caches, selectable by group of ways -- Single-... |
| Description |
RISC Microprocessor Hardware Specifications
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| File Size |
1,046.59K /
52 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
MPC862ED MPC862EC
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| OCR Text |
...ddress lines Memory controller (eight banks) -- Contains complete dynamic RAM (DRAM) controller -- Each bank can be a chip select or RAS to support a DRAM bank -- Up to 30 wait states programmable per memory bank -- Glueless interface to Pa... |
| Description |
Hardware Specifications
From old datasheet system
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| File Size |
475.98K /
88 Page |
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it Online |
Download Datasheet |
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Price and Availability
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