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Zarlink
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| Part No. |
MT90502 160
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| OCR Text |
...rough HDLC encapsulation. Three utopia Level 1 ports configurable as
Memory Bank A SSRAM (max: 1M x18) SDRAM (max: 8M x16)
DS5420 ISSUE 1 November 2001
Ordering Information MT90502AG 456 Pin Plastic BGA 0 to +70C PHY or ATM allowing fo... |
| Description |
Multi-Channel AAL2 SAR
From old datasheet system
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| File Size |
1,236.02K /
191 Page |
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it Online |
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Atmel corp
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| Part No. |
PC8260NBSP PC8260
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| OCR Text |
...ocal Bus (or PCI on PC8265) Two utopia Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can Support 8/16 bit Data Three MIL Interfaces Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3 Power Consumption: 2.5W ... |
| Description |
The versatile PC8260 PowerQUICC II is particularly useful in communication and networking applicatio
From old datasheet system
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| File Size |
283.76K /
53 Page |
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it Online |
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TI
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| Part No. |
TMS320C641
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| OCR Text |
...e 32-Bit General-Purpose Timers utopia [C6415T/C6416T] - utopia Level 2 Slave ATM Controller - 8-Bit Transmit and Receive Operations up to 50 MHz per Direction - User-Defined Cell Format up to 64 Bytes Sixteen General-Purpose I/O (GPIO) Pin... |
| Description |
FIXED-POINT DIGITAL SIGNAL PROCESSORS
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| File Size |
1,973.24K /
140 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
IDT77V106L200TFI IDT77V106L25
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| OCR Text |
...2mbps data rate ? ? ? ? ? 8-bit utopia level 1 interface ? ? ? ? ? 3-cell transmit & receive fifos ? ? ? ? ? receiver auto-synchronization and good signal indication ? ? ? ? ? led interface for status signalling ? ? ? ? ? supports utp categ... |
| Description |
3.3V ATM PHY for 25.6 and 51.2 Mbps
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| File Size |
217.05K /
27 Page |
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it Online |
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Conexant Systems
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| Part No. |
BT8223
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| OCR Text |
utopia or fifo interface cell fifo 4-port fifo interface microprocessor interface 52 control registers 28 status registors microprocessor address microprocessor data line overhead 78 8 8 8 8 8 8 16 hdlc data link cell generation tx rate con... |
| Description |
ATM Transmitter/Receiver
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| File Size |
1,001.38K /
161 Page |
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it Online |
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Zarlink
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| Part No. |
MT90503 161
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| OCR Text |
...d E1 Nx64 Service with CAS) Two utopia ports (Level 2, 16-bit, 50 MHz) with loopback function for dual fibre ring applications Third utopia port for connection to an external AAL5 SAR processor, or for chaining multiple MT90503 or other SAR... |
| Description |
2048VC AAL1 SAR
From old datasheet system
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| File Size |
1,521.61K /
232 Page |
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it Online |
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STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics, Inc.
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| Part No. |
STW51000 STW51000AT
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| OCR Text |
...rts Two Ethernet MAC One 16-bit utopia Level 2 Interface 32-bit General Purpose I/Os Two 32-bit Timers Programmable PLL Clock Generator IEEE-1149.1 (JTAG) Development tools available Baseband modem SW deliverables available
Figure 1. Pac... |
| Description |
SUPER INTEGRATED DSP ENGINE
From old datasheet system
GreenSIDE is a cost-effective, System-on-Chip device that targets applications in wireless infrastru
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| File Size |
202.83K /
8 Page |
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FREESCALE SEMICONDUCTOR INC
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| Part No. |
MPC8280VRQLDX MPC8280VRPKBX
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| OCR Text |
...16 16 ethernet (10/100) 3 3 3 3 utopia ii ports 0 0 2 2 multi-channel controllers (mccs) 1 1 1 2 pci bridge yes yes yes yes transmission convergence (tc) layer ? ? ? yes inverse multiplexing for atm (ima) ? ? ? yes universal serial bus (u... |
| Description |
32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
32-BIT, 300 MHz, RISC PROCESSOR, PBGA516
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| File Size |
1,273.87K /
80 Page |
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it Online |
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Price and Availability
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