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Cypress
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Part No. |
CY7C1371DV25-100AXC CY7C1373DV25-100BGXC
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OCR Text |
...re
Features
* No Bus Latency (nobl) architecture eliminates dead cycles between write and read cycles * Can support up to 133-MHz bus operations with zero wait states -- Data is transferred on every clock * Pin compatible and functionally... |
Description |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with nobl(TM) Architecture
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File Size |
441.68K /
31 Page |
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it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C1372AV25-167BGC
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OCR Text |
nobl? architecture cy7c1370av25 cy7c1372av25 cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 july 10, 2000 25 features ? zero bus latency, no dead cycles between write and read cycles fa... |
Description |
1M X 18 ZBT SRAM, 3.4 ns, PBGA119
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File Size |
348.58K /
26 Page |
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it Online |
Download Datasheet
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
CY7C1356A-166AC CY7C1354A-133BGCT
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OCR Text |
nobl? architecture cy7c1354a cy7c1356a cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05161rev. *e revised april 5, 2004 features ? zero bus latency?, no dead cycles between ... |
Description |
512K X 18 ZBT SRAM, 3.6 ns, PQFP100 256K X 36 ZBT SRAM, 4.2 ns, PBGA119
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File Size |
431.36K /
28 Page |
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it Online |
Download Datasheet
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Price and Availability
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