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Integrated Device Techn...
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Part No. |
ICS854S1208I
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OCR Text |
...fo r qa[0:3], nqa[0:3] outputs. lvcmos / lvttl interface levels. 3v ta p power power supply mode. see supply mode operation table on page 1. 4 clk0 input pulldown non-inverting differential clock input. 5nclk0input pullup/ pulldown invert... |
Description |
Eight differential LVDS output pairs
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File Size |
1,107.59K /
19 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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Part No. |
ICS854S01I
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OCR Text |
... frequency: 2.5ghz ? translates lvcmos/lvttl input signals to lvds levels by using a resistor bias network on npclk0, npclk1 ? rms additive phase jitter: 0.06ps (typical) ? propagation delay: 600ps (maximum) ? part-to-part skew: 350ps (max... |
Description |
One LVDS output pair
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File Size |
407.93K /
18 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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