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Qimonda
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| Part No. |
HYB18H512321BF-11/12/14 HYB18H512321BF-08/10
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| OCR Text |
...it is performed by setting cke asyn chronously high. exit of power down without self refresh is accomplished by setting cke high with a positive edge of clk. the value of cke is latched asynchronously by reset during power on to determin... |
| Description |
512-Mbit GDDR3 Graphics RAM
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| File Size |
1,340.22K /
43 Page |
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Infineon Technologies AG
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| Part No. |
HYB25D128800T-7 HYB25D128800T-7.5 HYB25D128800TL-6 HYB25D128800TL-7.5
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| OCR Text |
...for self refresh entry. ck e is asyn- chronous for self refresh exit. ck e must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and ck e are disabled during power-down. input buffers, excluding ck e , ... |
| Description |
128Mb (16Mx8) DDR 266A (2-3-3)
128Mb (16Mx8) DDR 266B (2.5-3-3)
16M X 8 DDR DRAM, 0.7 ns, PDSO66 0.400 INCH, PLASTIC, TSOP2-66
16M X 8 DDR DRAM, 0.75 ns, PDSO66 0.400 INCH, PLASTIC, TSOP2-66
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| File Size |
883.56K /
76 Page |
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it Online |
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Electronic Theatre Controls, Inc.
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| Part No. |
HYB25D512800AT-7 HYB25D512800AT-8 HYB25D512160AT-8 HYB25D512400AT-8 HYB25D512800AT-6
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| OCR Text |
...for self refresh entry. ck e is asyn- chronous for self refresh exit. ck e must be maintained high throughout read and write accesses. input buffers, excluding ck, ck and ck e are disabled during power-down. input buffers, excluding ck e , ... |
| Description |
512Mb (64Mx8) DDR266A (2-3-3)
512Mb (64Mx8) DDR200 (2-2-2)
512Mb (32Mx16) DDR200 (2-2-2)
512Mb (128Mx4) DDR200 (2-2-2)
512Mb (64Mx8) DDR333 (2.5-3-3) ？的512Mb4Mx8DDR333内存.5-3-3）？
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| File Size |
913.06K /
77 Page |
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it Online |
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Bourns, Inc.
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| Part No. |
PPC403GB-KA28C-1
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| OCR Text |
... fall into three basic classes: asyn- chronous imprecise exceptions, synchronous precise exceptions, and asynchronous precise exceptions. asynchronous exceptions are caused by events external to processor execu- tion, while synchronous e... |
| Description |
32-Bit Microprocessor 32位微处理
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| File Size |
364.34K /
44 Page |
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it Online |
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Silicon Storage Technology
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| Part No. |
SST39SF020
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| OCR Text |
...ion of the nonvolatile write is asyn- chronous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result... |
| Description |
2 Megabit (256K x 8) Multi-Purpose Flash
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| File Size |
287.60K /
23 Page |
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it Online |
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