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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1568KV18-550BZXC
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| OCR Text |
...t density (8m x 8, 8m x 9, 4m x 18, 2m x 36) 550 mhz clock for high bandwidth 2-word burst for reducing address bus frequency double data rate (ddr) interfaces (data transferred at 1100 mhz) at 550 mhz available in 2.5 clock cycle la... |
| Description |
72-mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
601.94K /
29 Page |
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