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SAMSUNG SEMICONDUCTOR CO. LTD.
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| Part No. |
S3C2510A
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| OCR Text |
... specification rev. 1.1 and pci mobile design guide ver. 1.1. and also it supports dma operation with two-channel dedicated dma to enhance ...sdram is used, this clock should be used sdram clock clksel u1 i phic clock select for cpu ... |
| Description |
16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example
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| File Size |
418.04K /
46 Page |
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Samsung Electronic
SAMSUNG[Samsung semiconductor]
SAMSUNG SEMICONDUCTOR CO. LTD.
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| Part No. |
K4S563233F K4S563233FHN K4S563233FHN75
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| OCR Text |
Mobile SDRAM in 90FBGA FEATURES
* 3.0V & 3.3V power supply. * LVCMOS compatible with multiplexed address. * Four banks operation. * MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -... |
| Description |
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
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| File Size |
138.59K /
12 Page |
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it Online |
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INTEGRATED SILICON SOLUTION INC
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| Part No. |
IS42SM16160D-10TL IS42SM32800D-75TL
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| OCR Text |
...800d 32mx8, 16mx16, 8mx32 256mb mobile synchronous dram preliminary information july 2009 features fully synchronous; all signals referenced...sdram are burst oriented. the 256mb mobile synchronous dram is designed to minimize current consum... |
| Description |
16M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54
8M X 32 SYNCHRONOUS DRAM, 5.4 ns, PDSO86
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| File Size |
428.14K /
25 Page |
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ICS
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| Part No. |
ICS9148-08
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| OCR Text |
...gic 0 level, when input low (In mobile mode, MODE=0)
SDRAM clock outputs. Supply for SDRAM (0:11), PLL core and 24,48MHz clocks, nominal 3.3V Data input for I2 C serial input. Clock input of I2 C input 24MHz output clock Pin 15, pin 46 fun... |
| Description |
Single Chip, Aladdin IV Clock with up to 83.3MHz
From old datasheet system
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| File Size |
581.27K /
14 Page |
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it Online |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS9148-75 ICS9148F-PPP-T ICS9148F-75-T AV9148F-75-T
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| OCR Text |
...gic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks... |
| Description |
Frequency generator and integrated buffers for mother board
Single Chip, 100MHz Aladdin V System Clock with Overclocking
From old datasheet system
Frequency Generator & Integrated Buffers for Mother Boards
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| File Size |
640.01K /
17 Page |
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it Online |
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Integrated Circuit Systems Inc
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| Part No. |
ICS9148F-36
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| OCR Text |
...gic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP(1:2) clocks... |
| Description |
CPU SYSTEM CLOCK GENERATOR,CMOS,SSOP,48PIN,PLASTIC
From old datasheet system
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| File Size |
576.80K /
16 Page |
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it Online |
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