| |
|
 |
XILINX
|
| Part No. |
XC2C32A
|
| OCR Text |
...nce and low power operation.
lvcmos standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible w...LVTTL lvcmos33 lvcmos25 lvcmos18 1.5V I/O
Supported I/O Standards
The CoolRunner-II 32 macrocell... |
| Description |
The CoolRunner-II 32-macrocell device
|
| File Size |
101.46K /
13 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
XILINX
|
| Part No. |
XC2C32
|
| OCR Text |
...nce and low power operation.
lvcmos standard is used in 3.3V, 2.5V, 1.8V applications. CoolRunner-II CPLDs are also 1.5V I/O compatible w...LVTTL lvcmos33 lvcmos25 lvcmos18 1.5V I/O
Supported I/O Standards
The CoolRunner-II 32 macrocell... |
| Description |
The CoolRunner-II 32-macrocell device
|
| File Size |
97.22K /
13 Page |
View
it Online |
Download Datasheet |
| |
|
|
ICS
|
| Part No. |
M2026
|
| OCR Text |
...LVPECL, as well as single-ended lvcmos, LVTTL Loss of Lock (LOL) output pin; Narrow Bandwidth control input (NBW pin) AutoSwitch (AUTO pin) - automatic (non-revertive) reference clock reselection upon clock failure Acknowledge pin (REF_A... |
| Description |
SAW PLL for Frequency Translation with automatic reference clock reselection, Loss of Lock indicator, and Hitless Switching options
|
| File Size |
333.73K /
12 Page |
View
it Online |
Download Datasheet |
| |
|
|
Xilinx Inc
|
| Part No. |
XC2C512-6PQ208C
|
| OCR Text |
...unner-II 512 macrocell features lvcmos, LVTTL, SSTL, and HSTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer an... |
| Description |
Complex PLD - Datasheet Reference
From old datasheet system
|
| File Size |
113.77K /
20 Page |
View
it Online |
Download Datasheet |
| |
|
|
NS
|
| Part No. |
DS90C385AM
|
| OCR Text |
...transmitter converts 28 bits of lvcmos/ LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fifth LVDS link. Every cycle of the... |
| Description |
3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz
|
| File Size |
628.65K /
14 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
