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Integrated Device Techn...
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| Part No. |
9DBV0741
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| OCR Text |
...output 4 dif6# out differential complementary clock output 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differe... |
| Description |
7-output 1.8V HCSL Fanout Buffer
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| File Size |
216.98K /
17 Page |
View
it Online |
Download Datasheet
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Integrated Circuit Syst...
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| Part No. |
9DBV0741
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| OCR Text |
...output 4 dif6# out differential complementary clock output 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differe... |
| Description |
Integrated terminations; save 28 resistors compared to standard HCSL outputs
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| File Size |
152.78K /
16 Page |
View
it Online |
Download Datasheet
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Integrated Device Techn...
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| Part No. |
9DBV0741AKILFT 9DBV0741AKLF 9DBV0741-17
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| OCR Text |
...utput. 4 dif6# out differential complementary clock output. 5 vddr1.8 pwr power supply for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. nominally 1.8v. 6 clk_in in tru... |
| Description |
7-Output 1.8V HCSL Fanout Buffer with Zo=100ohms
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| File Size |
207.88K /
17 Page |
View
it Online |
Download Datasheet
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Integrated Device Techn... Integrated Circuit Syst...
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| Part No. |
9DBV0731
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| OCR Text |
...output 4 dif6# out differential complementary clock output 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differe... |
| Description |
Spread Spectrum tolerant Spread Spectrum tolerant; allows reduction of EMI
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| File Size |
200.16K /
16 Page |
View
it Online |
Download Datasheet
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Integrated Device Techn...
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| Part No. |
9DBV0731AKLF 9DBV0731-16 9DBV0731AKILF
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| OCR Text |
...output 4 dif6# out differential complementary clock output 5 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 6 clk_in in true input for differe... |
| Description |
7-output 1.8V HCSL Fanout Buffer
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| File Size |
261.16K /
17 Page |
View
it Online |
Download Datasheet
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Price and Availability
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