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| Part No. |
MT41K256M4JP-125G
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| OCR Text |
...cific circuitry that is enabled/disabled is depend- ent upon the ddr3 sdram configuration and operating mode. taking cke low provides precharge power-down and self refresh operations (all banks idle) or ac- tive power-down (row active in an... |
| Description |
256M X 4 DDR DRAM, PBGA78
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| File Size |
446.14K /
21 Page |
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it Online |
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UTC
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| Part No. |
US211A US211B
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| OCR Text |
...age than v in when the output disabled (v en > 2v). enable input the switch will be disabled when the en pin is in a logic low/high condition. during this condition, the internal circuitry and mosfet are turned off, re ducing the su... |
| Description |
HIGH-SIDE POWER SWITCHES
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| File Size |
315.79K /
8 Page |
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it Online |
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Samsung Electronic
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| Part No. |
S3C7538
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| OCR Text |
...nput pins and are automatically disabled for output pins. ports 2 and 3 can be paired to enable 8-bit data transfer. 9 (3) 10 (4) 19 (13) 20 (14) tcl0 tcl1 d-4 p4.0 p4.1 p4.2 p4.3 p5.0?p5.3 i/o i 4-bit i/o ports. 1-bit and 4-bit read/write... |
| Description |
Single-Chip CMOS Microcontrollers
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| File Size |
257.46K /
34 Page |
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it Online |
Download Datasheet |
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