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  buffe Datasheet PDF File

For buffe Found Datasheets File :: 211    Search Time::3.234ms    
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    MC33998DW/R2 MC3399806

Freescale Semiconductor, Inc
Part No. MC33998DW/R2 MC3399806
OCR Text ...ply pin providing power for the buffe red sensor supplies and the drive circuitry for the 2.6 v linear power regulator. the v ddh pin is supplied from the switching regulator output, capable of providing 5.0 v @ 1400 ma total outpu...
Description Switching Power Supply with Linear Regulators

File Size 215.75K  /  20 Page

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    CLX2

Radiometrix Ltd
Part No. CLX2
OCR Text ...a identification and datastream buffe ring is conducted by the unit. there is no 'transmit enable' pin. synchronisation and fram ing words in the packet prevent the receiver outputting garbage in the absence of signal or presence of inte...
Description 19200 baud modem transceiver

File Size 173.51K  /  6 Page

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    CY7C1355C-133AXC

Cypress Semiconductor
Part No. CY7C1355C-133AXC
OCR Text ... internally self-timed output buffe r control to eliminate the need to use oe registered inputs for flow-through operation byte write capability 3.3 v / 2.5 v i/o power supply (v ddq ) fast clock-to-output times ? 6.5 ns (for 133-mhz ...
Description 9-Mbit (256 K × 36 / 512 K × 18) Flow-Through SRAM with NoBL Architecture

File Size 576.67K  /  33 Page

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    AT86RF231

ATMEL Corporation
Part No. AT86RF231
OCR Text ... ram for rx and tx (frame buffe r) buffers the data to be transmitted or the received data. two on chip low d ropout (ldo) voltage regulators provide the internal analog and digital 1.8v supply . ...
Description Low Power 2.4 GHz Radio Transceiver

File Size 1,091.47K  /  98 Page

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    Cypress
Part No. CY2PP318JI
OCR Text buffe r fastedge? series cy2pp318 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-07501 rev.*e revised july 27, 2004 features ? eight ecl/pecl differential outputs ? two ecl/...
Description 1 of 2:8 Differential Clock/Data Fanout buffer

File Size 162.77K  /  8 Page

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    CY7C1350G-133AXC CY7C1350G-133AXI CY7C1350G-133BGXC CY7C1350G-200AXC CY7C1350G-200AXI

Cypress Semiconductor
Part No. CY7C1350G-133AXC CY7C1350G-133AXI CY7C1350G-133BGXC CY7C1350G-200AXC CY7C1350G-200AXI
OCR Text ... internally self-timed output buffe r control to eliminate the need to use oe byte write capability 128 k 36 common i/o architecture 3.3 v power supply (v dd ) 2.5 v / 3.3 v i/o power supply (v ddq ) fast clock-to-output times ? 2...
Description 4-Mbit (128 K × 36) Pipelined SRAM with NoBL Architecture

File Size 476.99K  /  21 Page

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    ADSP-2137107

Analog Devices
Part No. ADSP-2137107
OCR Text ... engine m a i n tains circular buffe r s in exter- nal memory with tap/offset base d reads sdram accesses at 133 mhz and asy n chronou s accesses at 44.4 mhz 4 memory select lines a llows multiple extern a l memory dev i ces ...
Description SHARC? Processor

File Size 612.88K  /  48 Page

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    Micrel Semiconductor, Inc.
Part No. SY58611U
OCR Text ...tial output pair: differential buffe red output copy of the selected input signal. the output swing is typically 325mv. normally terminated 100 ? across the output (q and /q). see ?lvds output interface applications? subsection. 10, 11...
Description 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input 3.2Gbps速率精密的LVDS 2:1复用器,内置的终止和故障安全输入

File Size 607.55K  /  13 Page

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    CBTL05023

NXP Semiconductors
Part No. CBTL05023
OCR Text ...rail input voltage ? cmos input buffe r with hysteresis ? single 3.3 v 10 % power supply ? hvqfn24 3 mm 3 mm package, 0.4 mm pitch, with exposed center pad for thermal relief and electrical ground ? esd: 2500 v hbm, 1250 v cdm ? operati...
Description Multiplexer/demultiplexer switch for Thunderbolt applications

File Size 102.91K  /  4 Page

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    CY7C1352G-133AXC

Cypress Semiconductor
Part No. CY7C1352G-133AXC
OCR Text ... internally self-timed output buffe r control to eliminate the need to use oe byte write capability 256 k 18 common i/o architecture 3.3 v core power supply (v dd ) 2.5 v/3.3 v i/o power supply (v ddq ) fast clock-to-output times ...
Description 4-Mbit (256 K × 18) Pipelined SRAM with NoBL Architecture

File Size 409.34K  /  20 Page

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