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OM5303RT EPCQ64 2SB15 30344 IMH14A H40N60 MAX1562H 1N4729
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  sampled-data Datasheet PDF File

For sampled-data Found Datasheets File :: 14016    Search Time::1.532ms    
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    CMS4A16LAF

FIDELIX
Part No. CMS4A16LAF
OCR Text ...on input/output mask:l(u)dqm is sampled high and is an input mask signal for write accesses and an output disable signal for read accesses. input data is masked during a write cycle. the output buffers are placed in a high-z state (two-cl...
Description    128M(8Mx16) Low Power SDRAM

File Size 622.38K  /  46 Page

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    ICM107 ICM-107BPA ICM107B

ETC[ETC]
Part No. ICM107 ICM-107BPA ICM107B
OCR Text ...to 30 frames per second and sub-sampled quarter mega pixel resolution, operating at higher frame rate in progressive manner. Each pixel is c...data can be adjusted separately for the 4 Bayer pattern pixels. The output format is 10-bit raw data...
Description ICM107B Mega pixel Color CMOS image sensor

File Size 514.81K  /  20 Page

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    MT9VDDT3272A MT9VDDT3272AG

Micron Technology
Part No. MT9VDDT3272A MT9VDDT3272AG
OCR Text ...s and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dqs and dqs) is referenced to the crossings of ck and ck#. 21 cke0 input clock enable: cke activates (high) and dea...
Description    DDR SDRAM UNBUFFERED DIMM

File Size 533.69K  /  27 Page

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    MT5VDDT3272A MT5VDDT3272AG

Micron Technology
Part No. MT5VDDT3272A MT5VDDT3272AG
OCR Text ...e re spective device bank. a10 sampled during a precharge comman d determines whether the precharge applies to one device bank (a10 low, d...data (dq and dqs) is referenced to the crossings of ck and ck#. cke1 input clock enable: cke (regi...
Description    DDR SDRAM UDIMM

File Size 195.43K  /  12 Page

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    Alliance Semiconductor ...
Part No. AS4C64M16MD2-25BCN
OCR Text ... data rate (ddr) ca inputs are sampled on both positive and negative edge of ck. single data rate (sdr) inputs, cs# and cke, are sampled at the positive clock edge. clock is defined as the differential pair, ck and ck #. the positive cl...
Description    Configurable Drive Strength

File Size 5,405.98K  /  129 Page

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    Alliance Semiconductor ...
Part No. AS4C64M16MD1
OCR Text ...xcept dqs and dms are sampled on the rising edge of c lk. cke input level active high activates the cl...data input/output pins operate in the same manner as conventional drams. ba0, ...
Description    AS4C64M16MD1

File Size 1,110.88K  /  41 Page

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    Alliance Semiconductor ...
Part No. AS4C64M16D2-25BIN AS4C64M16D2-25BCN
OCR Text ...sdram input sign als are sampled on the crossing of positive edge of ck and negative edge of ck#. output (read) data is referenced to the crossings of ck and ck# (both directions of crossing). ...
Description    1Gb (64M x 16 bit) DDRII Synchronous DRAM (SDRAM)
   JEDEC Standard Compliant

File Size 1,456.99K  /  58 Page

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