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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1277V18-300BZC CY7C1266V18-300BZXC CY7C1266V18-333BZC CY7C1266V18-333BZXC
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| OCR Text |
...lock cycles two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only echo clocks (cq and cq ) simplify data captu...byte write select 0, 1, 2, and 3, active low . sampled on the rising edge of the k and k clocks du... |
| Description |
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 9 DDR SRAM, 0.45 ns, PBGA165
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) 4M X 8 DDR SRAM, 0.45 ns, PBGA165
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| File Size |
449.61K /
27 Page |
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it Online |
Download Datasheet
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NEC[NEC]
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| Part No. |
UPD44321361GF-A75 UPD44321181 UPD44321181GF-A75
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| OCR Text |
...Date Published April 2005 NS CP(K) Printed in Japan
The mark shows major revised points.
2002, 2005
PD44321181, 44321361
Ordering In...Byte Write Enable Input Asynchronous Output Enable Input Clock Input Synchronous Clock Enable Input ... |
| Description |
32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
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| File Size |
289.51K /
24 Page |
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it Online |
Download Datasheet |
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Price and Availability
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