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MC145003FU

MC145003FU DataSheet Motorola, Inc 128 Segment LCD Drivers

Segment Drivers

Motorola,

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MC145003FU MC145004FU MC145003FU

MC145003FU	[Motorola, Inc] 128 Segment LCD Drivers
MC145003FU	[MOTOROLA[Motorola Inc]] 128 Segment LCD Drivers
MC145003	[Motorola, Inc] 128 SEGMENT LCD DRIVERS CMOS
MC145003FU	[MOTOROLA[Motorola, Inc]] 128 SEGMENT LCD DRIVERS CMOS

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MC145003/D
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CMOS
128 Segment LCD Drivers
The MC145003/5004 are 128-segment, multiplexed-by-four LCD Drivers. The two devices are functionally the same except for their data input protocols. The MC145003 uses an SPI data input protocol which is directly compatible with that of the MC6805 family of microcomputers. Using a minimal amount of software (see example), the device may be interfaced to the MC68HCXX product families. The MC145004 has a IIC interface and has essentially the same protocol, except that the device sends an acknowledge bit back to the transmitter after each eight-bit byte is received. MC145004 also has a "read mode", whereby data sent to the device may be retrieved via the IIC bus. The MC145003/MC145004 drives the liquid-crystal displays in a multiplexed-by-four configuration. The device accepts data from a microprocessor or other serial data source to drive one segment per bit. The chip does not have a decoder, allowing for the flexibility of formatting the segment data externally. Devices are independently addressable via a two-wire (or three-wire) communication link which can be common with other MC145003/MC145004 and/or other peripheral devices. * Drives 128 Segments Per Package * Devices May Be Cascaded for Larger LCD Applications * May Be Used with the Following LCDs: Segmented Alphanumeric, Bar Graph, Dot Matrix, Custom * Quiscent Supply Current: 85 A @ 2.8 V VDD * Operating Voltage Range: 2.8 to 5.5 V * Operating Temperature Range: - 40 to 85C * Separate Access to LCD Drive Section's Supply Voltage to Allow for Temperature Compensation * See Application Notes AN1066 and AN442 BLOCK DIAGRAM
VLCD OSC1 OSC2 OSCILLATOR DRIVERS DRIVERS BP1-BP4 FP1-FP32
MC145003 MC145004
QFP FU SUFFIX CASE 848B
52
1
ORDERING INFORMATION
MC145003FU MC145004FU QFP QFP
PIN ASSIGNMENT
NC OSC1 OSC2 V DD BP1 BP2 BP3 BP4 A0 A1 A2 ENB NC FP32 FP31 FP30 FP29 FP28 FP27 FP26 FP25 FP24 FP23 FP22 FP21 FP20 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 NC FP19 FP18 FP17 FP16 FP15 V LCD VSS FP14 FP13 FP12 FP11 NC Din DCLK FS FP1 FP2 FP3 FP4 FP5 FP6 FP7 FP8 FP9 FP10
NC = NO CONNECTION
FS
FRAME SYNC GENERATOR POR DATA AND ADDRESS CONTROL AND TIMING
DCLK Din A0 A1 A2 ENB
LCD VOLTAGE WAVEFORM AND TIMING GENERATOR
128 - 32 MULTIPLEX
128-BIT LATCH
128-BIT SHIFT REGISTER
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) Motorola, Inc. 1994
REV 1 12/94
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol VDD Vin Vin osc Iin Tstg Parameter DC Supply Voltage Input Voltage, Din, and Data Clock Input Voltage, OSCin of Master DC Input Current, per Pin Storage Temperature Range Value - 0.5 to + 6.5 - 0.5 to 15 - 0.5 to VDD + 0.5  10 - 65 to + 150 Unit V V V mA C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Descriptions section.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic Ch ii Output Drive Current -- Frontplanes VO = 0.15 V VO = 2.65 V VO = 1.72 V VO = 1.08 V VO = 0.15 V VO = 5.35 V VO = 3.52 V VO = 1.98 V Supply Currents (fOSC) = 110 kHz IDD = Quiescent @ Iout = 0 A ILCD = Quiescent @ Iout = 0 A IDD = Quiescent @ Iout = 0 A ILCD = Quiescent @ Iout = 0 A Input Current Input Capacitance Frequencies OSC2 Frequency @ R1; R1 = 200 k FS Frequency @ R1 FS Pulse @ R1 BP Frequency @ R1 OSC2 Frequency @ R2; R2 = 996 k Average DC Offset Voltage (BP Relative to FP) Input Voltage "0" Level "1" Level fOSC2 fFS fFS fBP fOSC2 VOO VIL VIL VIH VIH 5 5 5 5 5 5 2.8 5.5 2.8 5.5 5 5 5 5 5 2.8 5 5 5 5 103 100 4.7 100 22.5 - 50 -- -- -- -- 111 110 5 110 24.5 + 50 -- -- -- -- 100 100 3.6 100 23 - 50 -- -- 2 3.85 150 140 5.6 140 33 + 50 0.85 1.65 -- -- 123 120 3.5 120 28 - 50 -- -- -- -- 136 133 3.9 133 31 + 50 -- -- -- -- (continued) kHz Hz s Hz kHz mV V IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IFH IFL IDDQ ILCDQ IDDQ ILCDQ Iin Cin 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2.8 -- 5.5 -- -- -- 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 -- 2.8 -- 5.5 -- -- 360 360 - 320 - 320 - 95 -- 90 -- 600 600 - 490 - 490 - 100 -- 100 -- -- -- -- -- -- -- -- -- -- -- -- - 1.5 -- 2 -- -- -- -- -- - 1.5 -- 1.5 65 30 350 60 -- -- 260 260 - 240 - 240 - 40 -- 40 -- 600 600 - 520 - 520 - 35 -- 55 -- -- -- -- -- - 0.1 -- -- -- -- -- -- - 1.5 -- 2 -- -- -- -- -- - 1.5 -- 1 140 45 1050 90 0.1 7.5 240 240 - 240 - 240 - 60 -- 55 -- 580 580 - 520 - 520 - 50 -- 70 -- -- -- -- -- -- -- -- -- -- -- -- -1 -- 1 -- -- -- -- -- -1 -- 1 A 85 20 350 35 -- -- A pF Symbol S bl VDD V VLCD V - 40C Min Max 25C Min Max 85C Min Max Unit Ui A
MC145003 * MC145004 2
MOTOROLA
ELECTRICAL CHARACTERISTICS (Continued)
VDD V 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3 5 3 5 3 5 3 5 3 5 3 5 3 5 3 VLCD V 2.8 2.8 2.8 2.8 2.8 2.8 2.8 2.8 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 40C Min - 290 - 290 310 310 90 -- - 90 -- - 490 - 490 600 600 100 -- - 100 -- Max -- -- -- -- -- 1 -- - 1.5 -- -- -- -- -- 1.5 -- -1 25C Min - 240 - 240 260 260 40 -- - 40 -- - 520 - 520 600 600 55 -- - 35 -- 50 100 -- -- 0 0 30 60 10 20 10 20 50 100 10 20 Max -- -- -- -- -- 2 -- -1 -- -- -- -- -- 1 -- -1 -- -- 20 120 -- -- -- -- -- -- -- -- -- -- -- -- 85C Min - 240 - 240 230 230 55 -- - 60 -- - 520 - 520 580 580 70 -- - 50 -- Max -- -- -- -- -- 1 -- -1 -- -- -- -- -- 1 -- -1 ns s ns ns ns ns ns ns Unit Ui A
Characteristic Ch ii Output Drive Current -- Backplanes VO = 2.65 V VO = 0.15 V VO = 1.08V VO = 1.72 V VO = 5.35 V VO = 0.15 V VO = 1.98 V VO = 3.52 V Pulse Width, Data Clock DCLK Rise/Fall Time Setup Time, Din to DCLK Hold Time, Din to DCLK DCLK Low to ENB High ENB High to DCLK High ENB High Pulse Width ENB Low to DCLK High (Figure 1) (Figure 1) (Figure 2) (Figure 2) (Figure 3) (Figure 3) (Figure 3) (Figure 3)
Symbol S bl IBH* IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL IBH IBL tw tr, tf tsu th th trec tw tsu
NOTE: Timing for Figures 1, 2, and 3 are design estimates only. * For a time (t = 4/OSC FREQ.) after the backplane waveform changes to a new voltage level, the circuit is maintained in the high-current state to allow the load capacitances to charge quickly. The circuit is then returned to the low-current state until the next voltage change.
SWITCHING WAVEFORMS
VALID tf 90% CLK 50% 10% tw tw tr VDD GND CLK Din 50% tsu th 50% VDD GND VDD GND
Figure 1.
tw ENB 50% tsu CLK 50% FIRST CLK th trec LAST CLK tw VDD GND VDD GND
Figure 2.
Figure 3.
MOTOROLA
MC145003 * MC145004 3
FUNCTIONAL DESCRIPTION
The MC145003/MC145004 has essentially two sections which operate asynchronously from each other; the data input and storage section and the LCD drive section. The LCD drive and timing is derived from the oscillator, while the data input and storage is controlled by the Data In (Din), Data Clock (DCLK), Address (A0, A1, A2), and Enable (ENB) pins. Data is shifted serially into the 128-bit shift register and arranged into four consecutive blocks of 32 parallel data bits. A time-multiplex of the four backplane drivers is made (each backplane driver becoming active then inactive one after another) and, at the start of each backplane active period, the corresponding block of 32 bits is made available at the frontplane drivers. A high input to a plane driver turns the driver on, and a low input turns the driver off. Figure 4 shows the sequence of backplanes. Figure 5 shows the possible configurations of the frontplanes relative to the backplanes. When a backplane driver is on, its output switches from VLCD to 0 V, and when it is off, it switches from 1/3 VLCD to 2/3 VLCD. When a frontplane driver is on, its output switches from 0 V to VLCD, and when it is off, it switches from 2/3 VLCD to 1/3 VLCD. The LCD drive and timing section provides the multiplex signals and backplane driver input signals and formats the frontplane and backplane waveforms. It also provides a "frame sync" pulse which may be used in a system where many LCD drivers are cascaded, to synchronize the backplanes/frontplanes of all participating LCD drivers. The address pins are used in cascaded systems to uniquely distinguish one LCD driver from another (and from any other chips on the same bus) and to define one LCD driver as the "master" in the system. There must be one master in any system. The enable pin may be used as a third control line in the communication bus. It may be used to define the moment when the data is latched. If not used, then the data is latched after 128 bits of data have been received.
TIME FRAME FRAME SYNC PULSE VLCD
0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V
BP1
BP2
BP3
BP4
Figure 4. Backplane Sequence
MC145003 * MC145004 4
MOTOROLA
TIME FRAME FRAME SYNC PULSE VLCD FRAME SYNC PULSE
TIME FRAME VLCD
0V FP DATA BITS 4321 0000 VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V FP DATA BITS 4321 0001
0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V VLCD 2/3 (VLCD) 1/3 (VLCD) 0V
1000
1001
0100
0101
1100
1101
0010
0011
1010
1011
0110
0111
1110
1111
Figure 5. Frontplane Combinations
MOTOROLA
MC145003 * MC145004 5
PIN DESCRIPTIONS
A0-A2 Address Inputs (Pins 42-44) The devices have to receive a correct address before they will accept data. Three address pins (A2, A1, A0) are used to define the states of the three programmable bits of MC145003/MC145004's 8-bit address. The address is 0111vwxy where v, w, x represent A2, A1, and A0 respectively. Where v, w, x = 0, then A2, A1, and A0 should be tied to 0 V. Where v, w, x = 1, then A2, A1, and A0 should be tied to VDD. For systems where only one MC145003/MC145004 is used, the address pins must be tied to VDD. This defines the device as a master. Other configurations of the address pins (except 000*) defines a device to be a slave. For systems with more than one MC145003/MC145004 (cascaded application) one of the MC145003/MC145004 must have all of its address pins tied to VDD (this defines it as the master). The master is responsible for: 1. Supplying the oscillator input to all slaves. 2. Sending one frame sync pulse at the beginning of every BP1 (backplane 1) period to keep the MC145003/ MC145004 synchronized. 3. Supplying a common set of backplane signals to be shared by all participating devices in the cascaded system (if desired). NOTE
Note: In applications where the circuit will be isolated from external manual interference the system designer may take advantage of the self-programming feature. Upon power-on, address pins which are left open-circuit will be charged to VDD. However, care must be taken not to inadvertently discharge the pins after power-on since the address may then be lost. A similar feature is also available on the ENB pin.
DCLK, Din Data Clock and Data Input (Pins 38, 39) Address input and data input controls. See Data Input Protocol sections for relevant option. OSC1, OSC2 Oscillator Pins (Pins 51, 50) To use the on-board oscillator, an external resistor should be connected between OSC1 and OSC2 of the master device. Optionally, the OSC1 pin of the master device may be driven by an externally generated clock signal. The oscillator signal for any slave(s) in the system is provided by the master device by connecting the master's OSC2 pin to the slaves'(s) OSC2 pin(s). The slaves'(s) OSC1 pin(s) should be connected to ground. A resistor of 680 k connected between the master's OSC1 and OSC2 pins gives an oscillator frequency of about 30 kHz, giving approximately 30 Hz as seen at the LCD driver outputs. A resistor of 200 k gives about 100 kHz, which results in 100 Hz at the driver outputs. LCD manufacturers recommend an LCD drive frequency of between 30 Hz and 100 Hz. See Figure 6.
EXTERNAL RESISTOR VALUE 10 M
1M
100 k
10 k
1k
10 k
100 k
1M
10 M
OSCILLATOR FREQUENCY
CAUTION
The configuration A0, A1, A2 = 000 should not be used. This does not give a valid address and is reserved for Motorola's use only. All three address pins should never be tied to 0 V simultaneously. Any other combination of Master (111) plus six Slaves (110, 101, 100, 011, 010, 001) is allowed.
Figure 6. Oscillator Frequency vs Load Resistance (Approximate) FS Frame Sync (Pin 37) The frame sync pin (FS) is configured as an output on the master device and as an input on the slave device(s). The master device outputs a pulse on the FS pin once at the beginning of each BP1 (backplane 1) active period to keep all MC145003/MC145004s synchronized. FP1-FP32 Frontplane Drivers (Pins 36-27, 25-22, 19-15, 13-1) Frontplane driver outputs. BP1-BP4 Backplane Drivers (Pins 48-45) Backplane driver outputs. VLCD LCD Driver Supply (Pin 20) Power supply input for LCD drive outputs. May be used to supply a temperature-compensated voltage to the LCD drive section, which can be separate from the logic voltage supply, VDD.
ENB Enable Input (Pin 41) If the ENB pin is tied to VDD, the MC145003/MC145004 will always latch the data after 128 bits have been received. The latched data is multiplexed and fed to the frontplane drivers for display. If external control of this latching function is required (for example, in a cascaded application where multiplexing of new data may require a delay until all participating MC145003/MC145004 data is updated), then the ENB pin should be held low, followed by one high pulse on ENB when data display is required. (This may also be useful in a system where one MC145003/MC145004 is permanently addressed and only the last 128 bits of data sent are required to be latched for display). The pulse on the ENB pin must occur while DCLK is high.
MC145003 * MC145004 6
MOTOROLA
VDD Positive Power Supply (Pin 49) This pin supplies power to the main processor interface and logic portions of the device. The voltage range is 2.8 to 5.5 V with respect to the VSS pin. For optimum performance, VDD should be bypassed to VSS using a low inductance capacitor mounted very closely to these pins. Lead length on this capacitor should be minimized. VSS Ground (Pin 21) Common ground.
DATA INPUT PROTOCOL
Two-wire communication bus DCLK, Din; three-wire communication bus DCLK, Din, ENB. MC145003 -- SPI DEVICE (FIGURE 7) Before communication with an MC145003 can begin, a start condition must be set up on the bus by the transmitter. To establish a start condition, the transmitter must pull the data line low while the clock line is high. The "idle" state for the clock line and data line is the high state. After the start condition has been established, an eight-bit address should be sent by the transmitter. If the address sent corresponds to the address of (one of) the MC145003(s) then on each successive clock pulse, the addressed device will accept a data bit. If the ENB pin is permanently high, then the addressed MC145003's internal counter latches the data to be displayed after 128 data bits have been received. Otherwise, the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC145003, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case, the 129th rising DCLK edge, which normally would be used to set up the stop or start condition, is ignored by the MC145003 and data continues to be received on the 130th rising DCLK. The latch function continues to work as normal (i.e., data is be latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. Interfacing the MC145003 with the MC6805 family The MC145003 performs as a slave receiver in an SPI environment if the clock idle state has been defined to be "high" (SPICR5 = 1). In three-wire or four-wire SPI environments, the slave select wire (SPISS) can be used for the ENB pin on the MC145003 as described above. Note that in full duplex SPI environments, MC145003 only receives data, it does not re-transmit data. MC145004 -- IIC DEVICE (FIGURE 8) Before communication with an MC145004 can begin, a start condition must be set up on the bus by the controller. To establish a start condition, the controller must pull the data line low while the clock line is high.
After the start condition has been established, an eight-bit address should be sent by the controller followed by an extra clock pulse while the data line is left high. In this option, only the seven most significant bits of the address are used to uniquely define devices on the bus, the least significant bit is used as a read/write control: if the least significant bit is 0, then the controller writes to the LCD driver; if it is 1, then the controller reads from the LCD driver's 128-bit shift register on a first-in first-out basis. If the seven most significant address bits sent correspond to the address of (one of) the LCD driver(s) then the addressed LCD driver responds by sending an "acknowledge" bit back to the controller (i.e., the LCD driver pulls the data line low during the extra clock pulse supplied by the controller). If the least significant address bit was 0, then the controller should continue to send data to the LCD driver in blocks of eight bits followed by an extra ninth clock pulse to allow the LCD driver to pull the data line Din low as an acknowledgement. If the least significant address bit was 1, then the LCD driver sends data back to the controller (the clock is supplied by the controller). After each successive group of eight bits sent, the LCD driver leaves the data line high for one pulse. If the ENB pin is permanently high, then the addressed MC145004's internal counter latches the data to be displayed after 128 data bits have been received. Otherwise the control of this latch function may be overridden by holding the ENB line low until the new data is required to be displayed, then a high pulse should be sent on the ENB line. The high pulse must be sent during DCLK high (clock idle). To end communication with an MC145004, a stop condition should be set up on the bus (or another start condition may be set up if another communication is desired). Note that the communication channel to an addressed device may be left open after the 128 data bits have been sent by not setting up a stop or a start condition. In such a case the rising DCLK edge which comes after all 128 data bits have been sent and after the last acknowledge-related clock pulse has been made is ignored; data continues to be received on the following DCLK high. The latch function continues to work as normal (i.e., data is latched either after each block of 128 data bits has been received or under external control as required). At any time during data transmission, the transfer may be interrupted with a stop condition. Data transmission may be resumed with a start condition and resending the address. CASCADED OPERATION The master device supplies the oscillator input via its OSC2 pin to the slave devices via their OSC2 pin(s). It sends a frame sync pulse via its FS pin to the slaves via their FS pins at the beginning of every BP1 valid time. In Figure 9, the ENB pins are tied together and used as a chip enable to latch the new data -- the ENB pins could have been tied to VDD if it were desirable to use the internal data bit counter to latch the new data. The four backplane inputs may come from the master only, with the slave backplanes being left open, as shown in Figure 6, or if more drive is required, then the slaves' backplanes may be connected to the corresponding backplanes of the master. Example: at room temperature, with a drive frequency of 30 Hz, around four to five MC145003/MC145004s may be used in a system where only the master's backplanes are connected to the LCD. For applications with heavier loads (e.g., large liquid crystals) or high drive frequencies or at high temperatures, the dc voltage component seen by the LCD may be kept to a minimum by connecting the corresponding backplanes of all participating MC145003/MC145004s together.
MOTOROLA
MC145003 * MC145004 7
D in FP1 FP2
A2
A1
A0
BP4
BP3 BP2
BP1 BP4
BP3 BP2
BP1
MC145003 * MC145004 8
129TH DCLK HIGH: (DOES NOT SHIFT DATA) 8-BITS ADDRESS 128-BITS DATA START
DCLK
START
ENB (IF USED)
ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH.
Figure 7. MC145003 (SPI DEVICE) Figure 7a. Data Input -- MC145003
BP D in x
* * *
4 32 14 3 21432 14 32 14 3 21432 1
4321
FP1 x: 1 (BPi, FPj) ON 0 (BPi, FPj) OFF
FP2
FP3
FP4
FP5
FP6
FP32
MOTOROLA
Figure 7b. Serial 128 Bits Data
WRITE TO LCD DRIVER (LOW-ORDER BIT = 0) A2 ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE A1 A0 BP4 BP3 BP2 BP1 BP4 BP3 BP2 BP1 LEFT HIGH BY CONTROLLER FP1 FP2 LEFT HIGH BY CONTROLLER
MOTOROLA
8-BITS ADDRESS 8-BITS DATA CONTINUES TO CLOCK DATA AND ACKNOWLEDGE PULLED LOW BY DRIVER PULLED LOW BY DRIVER (LOW-ORDER BIT = 1) ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE ENTIRE CLK FOR ACKNOWLEDGE 8-BITS ADDRESS ADDRESS ACKNOWLEDGED BY DRIVER 8-BITS DATA CONTINUES TO CLOCK DATA AND ACKNOWLEDGE LEFT HIGH BY DRIVER
D in (FROM CONTROLLER)
LAST DCLK PULSE (DOES NOT SHIFT DATA)
DCLK
START
D in (FROM LCD DRIVER) STOP ENABLE PULSE MAY OCCUR AS REQUIRED; BUT MUST BE DURING DCLK HIGH.
ENB (IF USED)
READ FROM LCD DRIVER
Figure 8. Data Input MC145004 (IIC Device)
D in (FROM CONTROLLER) LAST DCLK PULSE (DOES NOT SHIFT DATA)
DCLK STOP
START
D in (FROM LCD DRIVER) LEFT HIGH BY DRIVER
MC145003 * MC145004 9
LIQUID CRYSTAL DISPLAY FP33-FP64 FP1-FP32 FP21 FP20 FP22 FP24 FP23 FP25 FP27 FP26 FP28 FP29 FP30 FP31 FP32 FP20 FP21 FP22 FP23 FP24 FP25 FP26 FP27 FP28 FP29 FP30 FP1-FP32 FP1-FP32 BP1-BP4 FP31 FP32 680 k  OSC1 OSC2 V DD BP1 BP2 LCD DRIVER (MASTER) BP3 BP4 A0 A1 A2 ENB Din FS FP9 FP8 FP7 FP6 FP5 FP4 FP3 FP2 FP1 DCLK BP1-BP4
MC145003 * MC145004 10
OSC1 OSC2 V DD FP17 FP16 FP15 VLCD BP1 BP2 BP3 BP4 A0 A1 A2 ENB Din FS FP8 FP6 FP7 FP5 FP3 FP4 FP2 FP1 FP10 DCLK VSS FP14 FP13 FP12 FP11 FP19 FP18 FP19 FP18 FP17 FP16 FP15 VLCD LCD DRIVER (SLAVE) VSS FP14 FP13 FP12 FP11 FP9 FP10
CONTROLLER
Figure 9. Cascading Example
TO OTHER CHIPS ON BUS
SS CLOCK DATA
V DD VLCD VSS
MOTOROLA
APPLICATION INFORMATION
Figure 10 shows an interface example. Example 1 shows a semi-automatic SPI Mode (only start and stop conditions are done in non-SPI Mode). Example 2 contains the software to use HC11 with MC145003 in manual SPI Mode. Both examples use the same hardware connection.
VDD 1 k A0 A1 A2
VDD
MOSI MC68HC11 SCK SS
OSC1 Din DCLK ENB MC145003 OSC2 R = 470 k
BP1-BP4
FP1-FP32
1/4 MUX DISPLAY
Figure 10. Interface Example Between MC68HC11 and MC145003
CPOL = 0 CPHA = 0 SPI Off EW = 0 Setup Start Condition with SPI off (Write Data Port to 0) SPI On < ldaa $73, staa $1028 Send Address Byte $7E Send 16 bytes of Data SPI Off < ldaa $33, staa $1028 DATA = 0 SPI Off ENB = 1 Allows the latch of data to the FP outputs CLK = 1 DATA = 1 Stop Condition
Example 1. Semi-Automatic SPI Method
MOTOROLA
MC145003 * MC145004 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
0000 0000 0000 0000 0000 0000 0000
T T T T T T T
;=======CONSTANTS================================================= extram equ $A000 ;$A000 for 8K RAM stack equ $00FF ;last RAM byte intofs equ $1000 ;Internal Registers data equ $08 clock equ $10 enable equ $20 portd equ 8
A000 A000 A003 A005 A008 A00A A00D A010 A010 A014 A018 A01B A01D A020 A025 A026 A027 A029 A02D A030 A031 A033 A036 A03A A03E A042 A046 A048 A04B A04C A04E A051 A055 A059 A05D A05E A05F A060 A061 A062 A063 A064 A065 A066 A067 A068 A069 A06A A06B A06C A06D A06E A06F
T N M T M N T T U J T X T L H H R J T H M T J J J J M T H M T J J J H T T T T T T T T T T T T T T T T T H
8E00FF 8638 B71009 C611 CEA05E BDA010
;=======PROGRAM BEGIN============================================= org extram ;Program into RAM cold lds #stack ;set stack pointer ldaa #$38 ;set of MOSI,SS,SCK staa $1009 ;DDRD ldab #17 ldx #send jsr spi end cold spi ldy bclr jsr ldaa staa brclr inx decb bne bset jsr rts ldaa staa bset bset bclr bclr ldaa staa rts ldaa staa bclr bset bset rts fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb fcb rts #intofs portd,y #enable start 0,x $102A $29,y,#$80,*
18CE1000 181D0820 BDA031 A600 B7102A 181F2980FB 08 5A 26F2 181C0820 BDA04C 39 8633 B71028 181C0808 181C0810 181D0808 181D0810 8673 B71028 39 8633 B71028 181D0808 181C0810 181C0808 39 7E F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 F0 39
again
;EN = 0 ;start condition ;SPI Mode Use ;SPDR ;next DATA
again portd,y #enable stop
;stop condition
start
#$33 $1028 portd,y portd,y portd,y portd,y #$73 $1028
#data #clock #data #clock
;Normal Mode ;SPCR ;DATA = 1 ;CLK = 1 ;DATA = 0 ;CLK = 0 ;SPI Mode ;SPCR ;Normal Mode ;SPCR ;DATA = 0 ;CLK = 1 ;DATA = 0
stop
#$33 $1028 portd,y #data portd,y #clock portd,y #data
send
$007E $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0 $00f0
;LCD Driver Address ;Data to sent
;=======PROGRAM END===============================================
Example 2. Manual Method
MC145003 * MC145004 12
MOTOROLA
PACKAGE DIMENSIONS
QFP FU SUFFIX CASE 848B-02 L
39 27
S
D
S
0.20 (0.008) M H A-B 0.05 (0.002) A-B
-AL
-DB
V
DETAIL A
52 14
0.20 (0.008)
M
C A-B
S
D
S
40
26
B
1 13
-DB 0.20 (0.008) M H A-B 0.05 (0.002) A-B V 0.20 (0.008)
M S
B D
S
-A,B,DDETAIL A
S
C A-B
D
S
F C E -H-CSEATING PLANE DATUM PLANE
M
DETAIL C J N
H
0.10 (0.004) G M 0.02 (0.008)
M
BASE METAL D C A-B
S
D
S
SECTION B-B
MILLIMETERS MIN MAX 10.10 9.90 10.10 9.90 2.45 2.10 0. 38 0.22 2.10 2.00 0.33 0.22 0.65 BSC 0.25 -- 0.23 0.13 0.95 0.65 7.80 REF 10 5 0.13 0.17 0 7 0.13 0.30 12.95 13.45 0.13 -- 0 -- 12.95 13.45 0.35 0.45 1.6 REF INCHES MIN MAX 0.390 0.398 0.390 0.398 0.083 0.096 0.009 0.015 0.079 0.083 0.009 0.013 0.026 BSC 0.010 -- 0.005 0.009 0.026 0.037 0.307 REF 10 5 0.005 0.007 0 7 0.005 0.012 0.510 0.530 0.005 -- 0 -- 0.510 0.530 0.014 0.018 0.063 REF
U
T
DATUM PLANE
-H-
R Q K W X DETAIL C
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
DIM A B C D E F G H J K L M N Q R S T U V W X
MOTOROLA
MC145003 * MC145004 13
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MC145003 * MC145004 14

CODELINE TO BE PLACED HERE
*MC145003/D*
MC145003/D MOTOROLA