CXL1501M CMOS-CCD Signal Processor For the availability of this product, please contact the sales office. Description The CXL1501M is a CMOS-CCD signal processor designed for 8-mm VCR video signal processing. In combination with the 8-mm VCR video Y/C signal processing IC CXA1200Q, this IC configures a comb filter for Y/C separation in recording an image and elimination of crosstalk in playing back. Features * Single power supply 5V * Low power consumption 225mW (Typ.) * Built-in peripheral circuits * Completely adjustment free * Built-in quadruple progression PLL circuit * For NTSC signals Functions * 1H comb filter output * Dropout compensation (D.O.C) output * Delay time matching through output (THR) * PLL circuit (quadruple progression) * Clock driver * Autobias circuit * Sync tip clamp circuit * Sample and hold circuit Structure CMOS-CCD 30 pin SOP (Plastic) Absolute Maximum Ratings (Ta = 25C) 6 V * Supply voltage VDD * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD 500 mW Recommended Operating Conditions (Ta = 25C) Supply voltage VDD 5 5% V Recommended Clock Conditions (Ta = 25C) * Input clock amplitude VCLK 0.4 to 1.0 Vp-p (0.5Vp-p Typ.) * Clock frequency fCLK 3.579545 MHz * Input clock waveform sine wave Input Signal Amplitude VSIG 571 mVp-p (Max.) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E71050-PS Block Diagram and Pin Configuration (Top View) VCO OUT ADJY VSS PC OUT CLK NC NC VDD TH CCD1 VCO IN VDD VSS 30 25 24 22 20 21 17 16 29 28 27 26 23 19 18 VCO 1/4 divider Phase comparator 1 2 Clock driver NC NC YD VSS VDD VSS ABN ABP VSS CCD2 ADJC CCD3 VGGA VGGB Y-YD -2- D D IH + D 3 4 7 8 5 6 9 10 11 12 Autobias circuit (N) Output circuit, S/H circuit Bias circuit (B) Output circuit, S/H circuit Autobias circuit (P) Output circuit, S/H circuit 1 2 13 14 VSS Bias circuit (A) 15 VSS CXL1501M CXL1501M Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VSS CCD2 ADJC ABN CCD3 NC VDD VSS NC ABP VGGA YD VSS VGGB Y-YD VSS VSS TH VDD ADJY NC VCO OUT NC VSS CLK VDD PC OUT VCO IN VSS CCD1 I/O -- I O O I -- -- -- -- O O O -- O O -- -- O -- O -- O -- -- I -- O I -- I GND Clock input 5V power supply (For digital) Phase comparator output VCO input GND Signal input 1 (Reverse phase signal) > 100k (at no clamp) 2k to 5k > 100k 4k to 40k VCO output Forward phase autobias DC output Gate bias (A) DC output D.O.C signal output (Reverse phase signal) GND Gate bias (B) DC output Comb filter signal output GND GND THR signal output (Forward phase signal) 5V power supply (For analog) Reverse phase CCD bias DC output 600 to 2k 40 to 500 2k to 10k 40 to 500 2k to 20k 2k to 10k 40 to 500 5V power supply (For clock driver) GND GND Signal input 2 (Reverse phase signal) Forward phase CCD bias DC output Reverse phase autobias DC output Signal input 3 (Forward phase signal) > 100k (at no clamp) 600 to 2k 2k to 20k > 100k (at no clamp) Description Impedance () -3- Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 3.579545MHz, VCLK = 500mVp-p sine wave) See the Electrical Characteristics Test Circuit. SW conditions 1 6 7 a -- -- 35 45 55 a b -- -- -- -5.0 c a b c a b c a b c a b a a b b b b b b b b -- b b b b b a a a b b a a a b b b a a a c a b c a b c c c c c a a a d d d -- -- -- -- -56 -52 dB 9 VIT VIC VID +0.5 -- -- 350 mVp-p 8 -- -- -- 0 3 7 degree 7 a c c -- -- -- 0 3 7 % 7 b b b VIT VIC VID -2.5 -0.25 -0.25 +0.25 -1.5 -0.5 dB 6 b b b VIT VIC VID -6.5 -0.25 -0.25 +0.25 -4.5 -2.5 dB 5 b b -3.0 b -1.0 dB 4 a a a b b b b b b a a a a -- -- -- 9 a a a a b b b b b b a a a a a 8 VBIAS1 VBIAS2 VBIAS3 a a a a c c c bc a bc a bc a f 5-staircase wave7 f f f 5-staircase wave7 f f -- No-signal input -- -- b b b -- b b b b b b a a a a a a a a a a a a a a a a a a a a a a a a a a b a a b a a b a a a b a a a b a a a b a a a a a a a a a a a a a a a a 2 3 5 4 Min. Unit mA Typ. Max. Bias conditions2 (V) Note 3 Item -- Symbol Test conditions1 Supply current IDD GLT 196.678kHz 500mVp-p sine wave Low frequency gain GLC GLD GHT 3.579545MHz 150mVp-p sine wave 196.678kHz 150mVp-p sine wave High frequency gain GHC GHD fT Frequency response fc 3.579545MHz -4- fD DGT Differential gain DGC DGD DPT Differential phase DPC DPD VPT S/H pulse coupling VPC VPD SNT S/N ratio SNC No-signal input9 -- CXL1501M SND SW conditions 1 6 7 9 8 VBIAS1 VBIAS2 VBIAS3 2 3 5 4 Min. Unit Note Typ. Max. Bias conditions2 (V) Item 3.579545MHz 200mVp-p sine wave de a a -- -- -27 a b b b b b 10 10 10 dB Symbol Test conditions1 Chroma comb depth min. gain 3.587412MHz 200mVp-p sine wave C-CD 10 -5- CXL1501M CXL1501M Notes) 1 Adjust the output amplitude of the inversion and the non-inversion amplifiers in the signal input block to an equal value, as well as the phase difference to a precise 180. Also set the clock and input signal frequency accurately. 2 VIT, VIC and VID are defined as follows: VIT, VIC and VID are input signal clamp levels. They clamps the Video signal sync tip level. They are the pin voltages at no-input signal for pins 30, 2 and 5, respectively. VIT Input (CCD1) 30 L1501 2 Input (CCD2) VIC 5 Input (CCD3) VID Testing of VIT, VIC and VID is executed with a voltmeter under the following SW conditions: SW conditions 1 -- -- -- 2 b b b 3 b b b 4 b b b 5 a a a 6 a a a 7 a a a 8 -- -- -- 9 -- -- -- 10 -- -- -- 11 -- -- -- Test point V1 V2 V3 Item VIT VIC VID As VIT, VIC and VID differ with each IC, they are to be tested respectively. 3 This is the IC supply current value during clock and signal input. 4 GLT, GLC and GLD are output gains of TH, Y-YD, and YD pins when a 500mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. (Example of calculation) GLT = 20 log TH pin output voltage [mVp-p] 500 [mVp-p] [dB] -6- CXL1501M 5 GHT, GHC, and GHD are output gains of TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2, and CCD3 pins respectively. Bias at input (VBIAS1, VBIAS2 and VBIAS3) is tested respectively at VIT - 0.25V, VIC - 0.25V and VID + 0.25V. (Example of calculation) GHT = 20 log TH pin output voltage [mVp-p] 150 [mVp-p] [dB] 6 Indicates the dissipation at 3.579545MHz in relation to 196.678kHz. From the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 196.678kHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins, and from the output voltage at TH, Y-YD and YD pins when a 150mVp-p, 3.579545MHz sine wave is simultaneously fed to same, calculation is made according to the following formula. The input block bias for VBIAS1, VBIAS2 and VBIAS3 is tested at VIT - 0.25V, VIC - 0.25V and VID + 0.25V, respectively. (Example of calculation) fT = 20 log TH pin output voltage (3.579545MHz) [mVp-p] TH pin output voltage (196.678kHz) [mVp-p] [dB] 7 The differential gain (DG) and the differential phase (DP), when the 5-staircase wave in the following figure is fed, are tested with a vector scope: 143mV 357mV 500mV 143mV 1H 63.56s CCD3 pin input waveform (the input waveform of CCD1 and CCD2 pins is the inverted waveform of the figure above.) 8 The internal clock component to the output signal during no-signal input and the leakage of that high harmonic component are tested. The input block bias is tested at VITV, VICV, and VID + 0.5V. Test value [mVp-p] -7- CXL1501M 9 The noise level of output signal at no-input signal is tested with a video noise meter in the Sub Carrier Trap mode at BPF 100kHz to 4MHz. Vn [Vrms] The signal component is determined either by testing the output voltage (the same test system as that of noise level) at input of 357mVp-p, 196.678kHz, or by performing calculation from the values of GLT, GLC, and GLD in accordance with the following formula. Vs [Vp-p] (Example of Vs calculation) VS-T = 0.357 x 10 GLT 20 (VS-T: TH output voltage) (Example of S/N ratio calculation) SNT = 20 log Vn-T (noise component) [Vrms] [dB] VS-T (signal component) [Vp-p] 10 C-CD is calculated in accordance with the following formula from the Y-YD pin output voltage when a 200mVp-p, 3.579545MHz sine wave is simultaneously fed to CCD1, CCD2 and CCD3 pins and from the YCD pin output voltage when a 200mVp-p, 3.587412MHz sine wave is simultaneously fed to same. The input block bias is set to VIT - 0.3V, VIC - 0.3V and VID + 0.3V, respectively. C-CD = 20 log CLOCK fsc (3.579545MHz) sine wave Y-YD pin output voltage (3.587412MHz) [mVp-p] [dB] Y-YD pin output voltage (3.579545MHz) [mVp-p] 0.4Vp-p to 1.0Vp-p (0.5Vp-p Typ.) -8- CXL1501M Electrical Characteristics Test Circuit 9V CLK fSC (3.579545MHz) 0.5Vp-p sine wave 1 SW5 196.678kHz 500mVp-p sine wave 196.678kHz 150mVp-p sine wave 3.579545MHz 150mVp-p sine wave 3.579545MHz 200mVp-p sine wave 3.587412MHz 200mVp-p sine wave 5-staircase wave 2.2 a b a 1M 120 4.7 82k 3.3 30 CCD1 c -1 d SW1 e a SW3 CCD2 CCD3 ADJC ABN NC NC 1M a VSS 1 VDD b SW6 b 29 VSS 28 VCO IN 27 PC OUT 0.01 26 VDD 25 CLK 24 VSS 23 NC 22 VCO OUT 21 NC 0.1 1.2k -1 a SW2 b 1 20 ADJY b 3.3 0.01 19 VDD 18 TH 17 VSS 16 VSS SW8 a b c a Oscilloscope SW9 b Spectrum analyzer 1 x3 Vector LPF scope x3 Noise BPF meter 2 VGGA VGGB ABP VSS NC Y-YD c 9V 1.2k d YD 12 1 2 1 3 1 4 5 6 7 8 9 10 11 13 14 15 f 0.01 3.3 1 1 1 9V 1.2k -1 a SW4 b 1 51k 51k 51k V1 V2 V3 -50 -50 0 6M Frequency [Hz] 14.3M 0 200 6M Frequency [Hz] 14.3M b a SW7 1M 5V [dB] 0 -3 1) LPF frequency response [dB] 0 -3 2) BPF frequency response VBIAS1 VBIAS3 VBIAS2 Application Circuit fSC 0.5Vp-p sine wave 1.2k TH output (Forward phase signal) 1 24 23 22 21 20 1 1M 0.1 2.2 120 4.7 82k 3.3 30 29 28 27 0.01 26 25 3.3 0.01 19 18 17 16 CCD1 input (Reverse phase signal) 1 CCD2 input (Reverse phase signal) 1.2k 1 2 1 3 1 4 5 6 7 8 9 10 11 12 13 14 15 Y-YD output 1M 0.01 3.3 9V 1M 1.8k 22 9V Transistor used PNP : 2SA1175 YD output (Reverse phase signal) Signal output 1.2k 1 1 1 1 CCD3 input (Forward phase signal) 5V 2SC403 4fsc 1.8k Composite video signal input When using pin 22 (4 x fsc output) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -9- CXL1501M Low frequency gain vs. Supply voltage -1 High frequency gain vs. Supply voltage -2 High frequency gain [dB] -3 Low frequency gain [dB] -4 -3 -5 -4 -6 -5 4.75 5.0 VDD - Supply voltage [V] 5.25 4.75 5.0 VDD - Supply voltage [V] 5.25 Frequency response vs. Supply voltage 10 Differential gain vs. Supply voltage Frequency response [dB] 0 8 Differential gain [%] 5.0 VDD - Supply voltage [V] 5.25 -1 6 -2 4 -3 2 4.75 0 4.75 5.0 VDD - Supply voltage [V] 5.25 Low frequency gain vs. Ambient temperature -1 High frequency gain vs. Ambient temperature -2 High frequency gain [dB] 0 20 40 60 Ta - Ambient temperature [C] -3 Low frequency gain [dB] -4 -3 -5 -4 -6 -5 0 20 40 60 Ta - Ambient temperature [C] - 10 - CXL1501M Frequency response vs. Ambient temperature Differential gain vs. Ambient temperature 10 Frequency response [dB] 0 8 -1 Differential gain [%] 40 60 0 20 Ta - Ambient temperature [C] 6 -2 4 -3 2 0 20 40 60 0 Ta - Ambient temperature [C] Chroma comb depth min. gain vs. Supply voltage -10 -10 Chroma comb depth min. gain vs. Ambient temperature Chroma comb depth min. gain [dB] -20 Chroma comb depth min. gain [dB] 5.00 VDD - Supply voltage [V] 5.25 -20 -30 -30 -40 -40 -50 4.75 -50 0 20 40 60 Ta - Ambient temperature [C] Frequency response (TH, YD Output) 0 0 Chroma comb response (Y-YD Output) -2 Gain [dB] -10 -4 Gain [dB] 10k 100k f - Frequency [Hz] 1M -20 -6 -30 -8 -40 3.57 3.58 f - Frequency [MHz] 3.59 - 11 - CXL1501M Package Outline Unit: mm 30PIN SOP (PLASTIC) + 0.4 18.8 - 0.1 30 16 + 0.4 2.3 - 0.15 0.15 + 0.2 0.1 - 0.05 10.3 0.4 + 0.3 7.6 - 0.1 9.3 0.3 1 0.45 0.1 15 1.27 + 0.1 0.15 - 0.05 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS SOP-30P-L01 LEAD TREATMENT SOP030-P-0375 LEAD MATERIAL SOLDER PLATING 42 ALLOY 0.7g EPOXY RESIN - 12 - 0.5 0.2