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CX74063-36

CX74063-36 DataSheet Skyworks Solutions Inc. RF TRANSCEIVER WITH POWER RAMPING CONTROLLER AND INTEGRATED CRYSTAL OSCILLATOR WITH 13 MHZ OUTPUT FOR MULTI-BAND GSM, GPRS, AND EDGE APPLICATIONS

TRANSCEIVER WITH POWER RAMPING CONTROLLER INTEGRATED CRYSTAL OSCILLATOR WITH OUTPUT MULTI-BAND GPRS, EDGE APPLICATIONS

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---Full Text Search Engine--- CX74063-36 Skyworks Solutions Inc.
---Full Text Search Engine--- TRANSCEIVER WITH POWER RAMPING CONTROLLER INTEGRATED CRYSTAL OSCILLATOR WITH OUTPUT MULTI-BAND GPRS, EDGE APPLICATIONS

CX74063-36 CX74063-34 CX74063-35 CX74063-3X

CX74063-26	[Skyworks Solutions Inc.] RF TRANSCEIVER FOR MULTI-BAND GSM, GPRS, AND EDGE APPLICATIONS WITH POWER RAMPING CONTROLLER AND INTEGRATED CRYSTAL OSCILLATOR WITH 26 MHZ OUTPUT
CX74063-36	[Skyworks Solutions Inc.] RF TRANSCEIVER WITH POWER RAMPING CONTROLLER AND INTEGRATED CRYSTAL OSCILLATOR WITH 13 MHZ OUTPUT FOR MULTI-BAND GSM, GPRS, AND EDGE APPLICATIONS
CX74063-34	[Skyworks Solutions Inc.] RF Transceiver with Power Ramping Controller and Integrated Crystal Oscillator with 13 MHz Output for Multi-Band GSM, GPRS, and EDGE Applications
CX74063-35	[Skyworks Solutions Inc.] RF Transceiver with Power Ramping Controller and Integrated Crystal Oscillator with 13 MHz Output for Multi-Band GSM, GPRS, and EDGE Applications
CX74063-3X	[Skyworks Solutions Inc.] RF Transceiver with Power Ramping Controller and Integrated Crystal Oscillator with 13 MHz Output for Multi-Band GSM, GPRS, and EDGE Applications

DATA SHEET
CX74063-3x: RF Transceiver with Power Ramping Controller and Integrated Crystal Oscillator with 13 MHz Output for Multi-Band GSM, GPRS, and EDGE Applications
APPLICATIONS
* GSM850, EGSM900, DCS1800, and PCS1900 handsets * GPRS handsets and modules * EDGE downlink support
DESCRIPTION
The CX74063-3x transceiver (including -34, -35, and -36 package options) is a highly integrated device for multi-band Global System for Mobile CommunicationsTM (GSMTM) or General Packet Radio Service (GPRS) applications. The device requires a minimal number of external components to complete a GSM radio subsystem. The CX74063-3x supports GSM850, EGSM900, DCS1800, and PCS1900 applications. The receiver also supports downlink Enhanced Data-Rate GSM Evolution (EDGE). The receive path implements a direct down-conversion architecture that eliminates the need for Intermediate Frequency (IF) components. The CX74063-3x receiver consists of three integrated Low Noise Amplifiers (LNAs), a quadrature demodulator, tunable receiver baseband filters, and a DCoffset correction sequencer. In the transmit path, the device consists of an In-phase and Quadrature (I/Q) modulator within a frequency translation loop designed to perform frequency up-conversion with high output spectral purity. This loop also contains a phase-frequency detector, charge pump, mixer, programmable dividers, and high power transmit Voltage Controlled Oscillators (VCOs) with no external tank required. With the integrated gain controller (and an integrator ), the device realizes the Power Amplifier Control (PAC) functionality when combined with a coupler, a Radio Frequency (RF) detector and a Power Amplifier (PA). The CX74063-3x also features an integrated, fully programmable, sigma-delta fractional-N synthesizer suitable for GPRS multi-slot operation. Except for the loop filter, the frequency synthesizer function, including a wideband VCO, is completely on-chip. The reference frequency for the synthesizer is supplied by the integrated crystal oscillator circuitry. The 56-pin 8x8 RF Land Grid Array (RFLGATM) device package and pin configuration are shown in Figure 1. A functional block diagram is shown in Figure 2. Signal pin assignments, functional pin descriptions, and equivalent circuitry are provided in Table 1.
FEATURES
* Direct down-conversion receiver eliminates the external image reject/IF filters * Three separate LNAs with single-ended inputs * RF gain range: GSM = 20 dB, DCS = 22 dB, PCS = 20 dB. Baseband gain range = 100 dB * Gain selectable in 2 dB steps * Integrated receive baseband filters with tunable bandwidth * Integrated DC offset correction sequencer * Reduced filtering requirements with translational loop transmit architecture * Integrated transmit VCOs * Wide RF range for quad band operation * Integrated PAC loop * Single integrated, fully programmable fractional-N synthesizer suitable for multi-slot GPRS operation * Fully integrated wideband Ultra High Frequency (UHF) VCO * Integrated crystal oscillator * Separate enable lines for power management transmit, receive, and synthesizer modes * Supply voltage down to 2.6 V * Band select and front-end enable states may be exercised on output pins to control external circuitry. * Low external component count * Optional bypass of baseband filtering for use with high dynamic range Analog to Digital Converters (ADCs) for current savings * Interfaces to low dynamic range ADC * Meets AM suppression requirements without baseband interaction. * 56-pin RFLGA 8x8 mm package (low temperature option, CX74063-34; high temperature option, CX74063-35 and CX74063-36) * Low power standby mode
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NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
TX1800/TX1900
TXVCO TUNE
VCCTXVCO
UHFTUNE
VCCUHF
UHFBYP
TX900
RXQN
RXQP
VCC4
VCC3
RXIN
RXIP
56
55
54
53
52
51
50
49
48
47
46
45
44
RXENA TXENA PCO VCXO_EN PDETVCC VCC1 TXCPO TXINP LNA900IN GNDLNA900 LNA1800IN PDET LNA1900IN NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
43 42 41 40 39 38 37 36 35 34 33 32 31 30
VDDBB
LE
CLK DATA XTALTUNE SXENA VCCFN_CP UHFCPO GNDFN XTAL VCCF VCCD GNDD XTALBUF LPFADJ
16
17
18
19
20
21
22
23
24
25
26
27
28 CAPQN
15
29
TXIFP
PAVAPC
BBVAPC
TXIFN
TXIP
CAPIP
TXIN
VCC2
CAPIN
TXQP
CAPQP
TXQN
C1328
Figure 1. CX74063-3x Pinout - 56-Pin RFLGA (8 x 8 mm) (Top View)
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Data Sheet I CX74063-34/-35/-36
PDETVCC
BBVAPC
TXIN TXQN TXIP TXQP
LE DATA CLK
PA GAIN CONTROLLER + - DET VCC Tx PATH TxIFP TxIFN OFFSET GEN GSM850/EGSM900 TX900
PAVAPC
PDET
PCO
TXINP
+
D2 PFD
CP TXCPO
TXVCOTUNE
FILTN FILTP
TX1800/TX1900
D1 DCS1800/PCS1900
Sx VCXO_EN XTAL Frac-N UHFTUNE XTALTUNE XTALBUF UHFCPO LO
Rx PATH
VGA2 RXIP RXIN
VGA1
GSM LNA LNA900IN
DCOC
DCOC
DCOC
CAPIP CAPIN
Indicates Off-chip
VGA2 RXQP RXQN
VGA1
DCS LNA LNA1800IN
DCOC
DCOC
DCOC
CAPQP CAPQN PCS LNA
LNA1900IN
C900
Figure 2. CX74063-3x Transceiver Block Diagram
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Data Sheet I CX74063-34/-35/-36
Table 1. CX74063-3x Signal Descriptions (1 of 5)
Pin #
1
Name
RXENA
Description
Receiver enable input
Equivalent Circuit
2
TXENA
Transmitter enable input
3
PCO
Bi-directional band select
4
VCXO_EN
VCXO enable pin
5
PDETVCC
Bias for the RF Detector
Vout Vref
6 7
VCC1 TXCPO
LNA and TX charge pump supply Translational loop charge pump output
VCC1
8
TXINP
Translational loop feedback input
9
LNA900IN
Low band LNA input for GSM850, EGSM900
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Data Sheet I CX74063-34/-35/-36
Table 1. CX74063-3x Signal Descriptions (2 of 5)
Pin #
10
Name
GNDLNA900
Description
Low band LNA emitter ground
Equivalent Circuit
11
LNA1800IN
DCS LNA input
12
PDET
Feedback Input to power control loop
13
LNA1900IN
PCS LNA input
14 15 16
NC NC PAVAPC
No connect No connect PA control output
No connect No connect
Vout
17
BBVAPC
PA control Baseband input
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NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
Table 1. CX74063-3x Signal Descriptions (3 of 5)
Pin #
18 19 20 21 22 TXIP TXIN TXQP TXQN TXFP
Name
Description
TX I baseband input positive TX I baseband input negative TX Q baseband input positive TX Q baseband input negative TX IF filter output positive
Equivalent Circuit
23
TXFN
TX IF filter output negative
24 25 26 27 28 29
VCC2 CAPIP CAPIN CAPQP CAPQN LPFADJ
RX mixer and TX loop supply Capacitor filter I positive Capacitor filter I negative Capacitor filter Q positive Capacitor filter Q negative LPF frequency setting resistor
VCC2
30
XTALBUF
Crystal oscillator buffer output
31
GNDD
Synthesizer digital ground
32 33 34
VCCD VCCF XTAL
Synthesizer digital supply Synthesizer analog supply and crystal oscillator supply Crystal input
VCCD VCCF
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Data Sheet I CX74063-34/-35/-36
Table 1. CX74063-3x Signal Descriptions (4 of 5)
Pin #
35
Name
GNDFN
Description
Synthesizer analog ground
Equivalent Circuit
36
UHFCPO
Synthesizer charge pump output
37 38
VCCFN_CP SXENA
Synthesizer charge pump supply Synthesizer enable input
VCCFN_CP
39
XTALTUNE
Crystal oscillator varactor control
40 41
DATA CLK
Serial bus data input Serial bus clock input
42 43 44
LE VDDBB UHFBYP
Serial bus latch enable input Digital CMOS supply Bypass capacitor for UHF VCO VDDBB
45
UHFTUNE
UHF VCO control input
46 47
VCCUHF VCC3
UHF VCO supply LO chain supply
VCCUHF VCC3
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Data Sheet I CX74063-34/-35/-36
Table 1. CX74063-3x Signal Descriptions (5 of 5)
Pin #
48 RXQN
Name
Description
Receiver output Q negative
Equivalent Circuit
49
RXQP
Receiver output Q positive
50
RXIN
Receiver output I negative
51
RXIP
Receiver output I positive
52 53 54
VCC4 VCCTXVCO TX900
Baseband supply Transmit VCO supply Low band transmit VCO
VCC4 VCCTXVCO
55
TX1800/TX1900
DCS and PCS transmit VCO output
56
TXVCOTUNE
Transmit VCO control input
Technical Description
The CX74063-3x transceiver contains the following sections, as shown in Figure 2. * Receive section. Includes three integrated LNAs, a quadrature demodulator section that performs direct down conversion, baseband amplifier circuitry with I/Q outputs, and three stages of DC offset correction. The receiver can be calibrated to optimize IP2 performance. * Synthesizer section. Includes an integrated on-chip VCO locked by a fractional-N synthesizer loop, and a crystal oscillator to supply the reference frequency. * Transmit section. The TX path is a translational loop architecture consisting of an I/Q modulator, integrated high power VCOs, offset mixer, programmable divider, PFD, and charge pump. The device also provides integrated gain controller for the PAC loop, plus the bias generator for an external diode detector.
A 3-wire serial interface controls the transceiver and synthesizer. The receiver gain control, as well as the division ratios and charge pump currents in the synthesizer and transmitter, can be programmed using 24-bit words. These 24-bit words are programmed using the 3-wire input signals CLK, DATA, and LE. To ensure that the data stays latched in power down mode, pin 43 (VDDBB) must be continuously supplied with voltage. This pin is provided for the digital sections to allow power supply operation compatible with modern digital baseband devices. The TXENA, RXENA, and SXENA signals separately enable the CX74063-3x transmitter, receiver, and synthesizer sections. TXENA and RXENA should be held low during programming. SXENA should be held high during the programming of the R3 IP2 Calibration Register. (These timing signals are detailed in Figures 9, 10, and 11.)
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Data Sheet I CX74063-34/-35/-36
Receive Section
LNA and Quadrature Demodulator Three separate LNAs are integrated to address different bands of operation. These LNAs have separate single-ended inputs, which are externally matched to 50 . The gain is switchable between high (i.e., 15 dB typical) and low (i.e., -5 dB GSM, -7 dB DCS, and -5 dB PCS typical) settings. The LNA outputs feed into a quadrature demodulator that downconverts the RF signals directly to baseband. Two external 470 pF capacitors are required at the demodulator output to suppress the out-ofband blockers. Baseband Section An off-chip capacitor and three fixed poles of on-chip, low pass filtering provide rejection of strong in- and out-of-band interferers. In addition, a tunable, four-pole gmC filter provides rejection of the adjacent channel blockers. Incorporated within the fixed-pole filters are two switchable gain stages of 18 dB and 12 dB gain steps, respectively. There is an additional programmable gain amplifier with a gain range from 0 to + 34 dB, selectable in 2 dB steps in the four-pole tunable filter. The final filter output feeds an amplifier with a gain range from 0 to 30 dB, selectable in 6 dB steps. There is an additional gain stage on the four-pole tunable filter output, the auxiliary gain stage, selectable at 0 dB or + 6 dB. The gain control ranges are shown in Figure 3. Recommended combinations of individual block gain settings are shown in Table 22 for GSM900, Table 23 for DCS1800, and Table 24 for PCS1900. For added baseband interface flexibility, the four-pole filter, its associated Variable Gain Amplifier (VGA), and DC offset correction loop can be bypassed and turned off for current savings. In Table 2 the typical locations of all eight receiver baseband poles are given. The final four poles are produced by the tunable gmC filter, as set by the external resistor (recommended value is 39.2 k, 1%) placed from pin 29 to ground. For these tunable poles, Table 2 gives the pole location as a function of this resistor.
DC Offset Correction Three DC offset correction (DCOC) loops ensure that DC offsets, generated in the CX74063-3x, do not overload the baseband chain at any point. After compensation, the correction voltages are held on capacitors for the duration of the receive slot(s). Internally, on-chip timing is provided to generate the track and hold (T_H) signals for the three correction loops. The timing diagram for the DC offset correction sequence with reference to the receive slot is shown in Figure 4. A rising edge on either the RXENA signal, selected via the serial interface, places the DC compensation circuitry in the track mode. The timing parameters for each of the three compensation loops, tt_H1, tt_H2, and tt_H3, and the time between compensation start and the LNA being turned on, tFEENA, are defined via an internal state machine. The state machine is preprogrammed with fixed default values, but may be readjusted via the serial interface. The timing parameters for the three compensation loops and the LNA power-up are each independently defined, relative to the compensation start. Therefore, they may be programmed to occur in any order, but the sequences shown in Figure 4 and Figure 5 are recommended. The device default timing is shown in Figure 5, with a total time of 60 s. Individual default timings are given in Table 17. For user-programmed timing, the total time may be set as short as approximately 10 s when FREF has a 13 MHz clock applied. However, the shortest recommended total time is approximately 30 s, since at the highest gain settings, the resulting DC may degrade as correction time is reduced. AM Suppression and IP2 Calibration For direct conversion GSM applications, it is imperative to have extremely low second-order distortion. Mathematically, second-order distortion of a constant tone generates a DCterm proportional to the square of the amplitude. A strong interfering amplitude-modulated (AM) signal is therefore demodulated by second-order distortion in the receiver front end, and generates an interfering baseband signal.
Table 2. Receive Pole Locations
Stage
Mixer + RC Filter
Typical Pole Location (rad/sec)
-1.0 x 10
6
Pole Type
Real (capacitors at pins 25-26 and 27-28 fixed at 470 pF) Real Conjugate Real (adjust with resistor at pin 29) Real (adjust with resistor at pin 29) Conjugate (adjust with resistor at pin 29)
-1.65 x 106 LPF1 VGA1 + gmC filter (-0.91 x 106)  j(1.35 x 106) (-0.91 x 10 ) x (39.2 k/R) (-0.91 x 106) x (39.2 k/R) [(-0.46 x 106)  j(1.0 x 106)] x (39.2 k/R)
6
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Data Sheet I CX74063-34/-35/-36
LNA
Mixer + RC Filter
LPF1
VGA1 + GMC Filter + Aux
VGA2
RXIP RXIN
RXQP RXQN
GSM LNA High Low 15 dB -5 dB
Mixer + RC Filter High Low 40 dB 22 dB
LPF1 High Low 10 dB -2 dB
VGA1 +GMC Max 30 dB
VGA2 Max 30 dB
...
(in 6 dB steps) DCS LNA High Low 15 dB -7 dB Additional Interstage Losses GSM900 PCS LNA High Low 15 dB -5 dB AUX High Low 6 dB 0 dB 4.2 dB DCS1800 5.0 dB PCS1900 6.2 dB VGA1 Fine Max Mid Min 4 dB 2 dB 0 dB Min 0 dB
... ...
(in 6 dB steps)
...
Min 0 dB
S092
Figure 3. Gain Control Settings
RXENA Hold mode (Loop 1)
DC Offset Correction Loop 1
Track mode tT_H1 (Note 1)
DC Offset Correction Loop 2
Track mode tT_H2 (Note 1)
Hold mode (Loop 2)
DC Offset Correction Loop 3
Track mode tT_H3 (Note 1)
Hold mode (Loop 3)
Front End Enable
(LNA off) tFEENA (Note 1)
(LNA on) Start of RX slot
Note 1. tT_H1, tT_H2, tT_H3, and tFEENA are programmed in Register 2.
101953A 3_012902
Figure 4. DC Offset Correction Timing (LNA Off During All of the DC Offset Correction Sequence)
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Data Sheet I CX74063-34/-35/-36
RXENA Hold mode (Loop 1)
DC Offset Correction Loop 1
Track mode tT_H1 (Note 1)
DC Offset Correction Loop 2
Track mode tT_H2 (Note 1)
Hold mode (Loop 2)
DC Offset Correction Loop 3
Track mode tT_H3 (Note 1)
Hold mode (Loop 3)
Front End Enable
(LNA off) tFEENA (Note 1)
(LNA on) Start of RX slot
Note 1. tT_H1, tT_H2, tT_H3, and tFEENA are programmed in Register 2.
101953A 4_012902
Figure 5. DC Offset Correction Timing (LNA On During Part of the DC Offset Correction Sequence)
A commonly used measure for receiver second-order distortion is the second-order intercept point, IP2. For example, to ensure that the unwanted baseband signals are 9 dB below the wanted signal required under the AM suppression test for type approval (see 3GPP TS 51.010-1), an input IP2 of 43 dBm is required: The CX74063-3x receiver includes a circuit that minimizes second-order distortion. This IP2 calibration circuit effectively compensates any second-order distortion in the receive chain that would otherwise generate unwanted baseband signals in the presence of strong interfering signals. When calibrated correctly, the CX74063-3x IP2 meets the GSM AM suppression test requirements in all bands with good margin. To calibrate IP2, apply a strong RF signal at the receiver input and observe the resulting DC voltage level change at the receiver I/Q outputs. The exact frequency and level of the signal applied for the purpose of the calibration are not critical. The signal should, however, be within the receive band, but at least 6 MHz offset from the frequency to which the receiver is tuned. The level should be high enough to cause a notable DC shift at the I/Q outputs. A recommended value is -30 dBm at the LNA input, which applies to all three LNAs. A set of I/Q compensation coefficients can then be programmed to the device to minimize the DC voltage shift resulting from the second-order distortion. When the DC due to the interfering signal is minimized, the IP2 performance is optimized. Note: SXENA, pin 38, must be held high, and a clock signal must be present on XTAL, pin 34, during the programming of the IP2 calibration coefficients in Register 3, see Table 18.
The IP2 calibration is a one-time factory calibration that should be done for each band and each individual device for optimum performance. The determined coefficients must be stored in nonvolatile memory and programmed to the CX74063-3x upon each power-up as part of device initialization. There are onchip registers that must be programmed through Register 3 with the appropriate IP2 coefficients for the band in use. As long as a supply voltage is maintained on pin 43, VDDBB, the IP2 coefficients for ILOWBAND, IHIGHBAND, QLOWBAND, QHIGHBAND, programmed to the device remain in the registers. After the supply voltage has been removed from VDDBB, the coefficients must be re-programmed to the device again. Receive/Transmit I/Q Baseband Signals. Separate pins are provided for receive I/Q outputs and transmit I/Q inputs. However, for basebands that multiplex these signals, the receive I/Q outputs and transmit I/Q inputs can be tied together.
Synthesizer Section
The CX74063-3x includes a fully integrated UHF VCO with an on-chip LC tank. A single sigma-delta fractional-N synthesizer can phase-lock the local oscillator used in both transmit and receive paths to a precision frequency reference input. Fractional-N operation offers low phase noise and fast settling times, allowing for multiple slot applications such as GPRS. The CX74063-3x frequency stepping function with a 3 Hz resolution allows triple band operation in both transmit and receive bands using a fully integrated single integrated on-chip UHF VCO. The fine synthesizer resolution allows direct compensation or adjustment for reference frequency errors.
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Data Sheet I CX74063-34/-35/-36 The fractional-N synthesizer consists of the following: * * * * * VCO High frequency prescaler N-divider with a sigma-delta modulator Reference buffer and divider Fast phase frequency detector and charge pump * f VCO =
3 f RX for DCS1800 and PCS1900 4
For the transmitter VCO frequency, refer to the equations shown in Figure 6. Digital Frequency Centering The CX74063-3x uses a novel technique whereby the UHF VCO frequency range is re-centered each time the synthesizer is programmed. This technique is called Digital Frequency Centering (DFC). The DFC technique: * Extends the VCO frequency coverage * Speeds up settling time * Ensures robust performance since the VCO is always operated at the center of its tuning range. Each time the synthesizer is programmed, the DFC circuit is activated, and the VCO is centered to the programmed frequency in less than 20 s. After this, normal Phase Locked Loop (PLL) operation is resumed and the fine settling of the frequency is finalized. The DFC typically adjusts the VCO center frequency to within a few MHz and no more than 5 MHz offset, and presets the tuning voltage to the center of the range before the PLL takes over. This speeds up frequency settling and ensures that the PLL control voltage never operates close to the rails.
The user must provide the following three parameters: * The reference divider value, from 1 to 15 * The N-divider value, in a manner similar to an integer-N synthesizer * A fractional ratio The generated frequency is given by the following equation:
FN    N + 3.5 + 22  f ref 2  = R
f VCO
where: fVCO N FN R fREF
= Generated VCO frequency = N-divider ratio integer part = Fractional setting = R-divider ratio = Reference frequency
UHF VCO Frequency Setting For the receiver, to tune the receive frequency, fRX, set the VCO frequency, fVCO, as follows: * f VCO =
3 f RX for GSM850/900 2
Phase Detect External Loop Filter
fTx Tx VCO
D2 Ext Tx I
+
D1
90o
L/C Filter
Tx Q
X2
where: fTx = fLO (2 D1 -- D2)/D1 GSM: fLO = (fVCO)/3 DCS/PCS: fLO = (2fVCO)/3 X2 Fractional-N PLL UHF VCO fVCO /3
C1308
Figure 6. Transmitter Frequency Generation
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Data Sheet I CX74063-34/-35/-36 The DFC is an adaptive circuit that corrects for any VCO center frequency errors caused by variations of the integrated VCO circuit, temperature, supply voltage, aging etc. The VCO can be centered at any frequency in the range from 1.2 GHz to 1.55 GHz. Once centered, the VCO has a minimum analog tuning range of 30 MHz. No calibration or data storage is needed for DFC operation. It is activated by one of two events: * When the synthesizer is programmed, the rising edge of the LE signal starts the DFC cycle and, * When changing the level of the SXENA signal from low to high, thereby turning on the synthesizer, the rising edge of the SXENA signal starts the DFC cycle. Crystal Oscillator A crystal oscillator is designed to provide the reference frequency for the synthesizer. As shown in Figure 7, the oscillator uses an external crystal to generate an accurate oscillation frequency. The reference frequency can be changed through coarse tuning with an integrated capacitor array or fine tuning with the integrated varactor diode. The coarse tuning is done by switching in and out (using a digital word programmed via the serial interface) the capacitor network (CAP_A and CAP_B) located at the input of the integrated buffer. The fine tuning is done by providing a tuning voltage to the integrated varactor diode. Table 20 describes the control bits. An output buffer is provided to drive the baseband circuitry (XTALBUF, pin 30). The VCXO and buffer circuitry are powered from pin 33 (VCCF). When VCCF is ramped to a voltage greater than 2.6 V, the output buffer powers on. The oscillator core powers up when pin 4 (VCXO_EN) is set to logic 1. If pin 4 is tied permanently to logic 1, the R6 VCXO Control Register is set to a defined state by a power-on reset. Pin 4 should be held
VCCF (Pin 33)
100 k
low if an external reference oscillator is used. The buffer may be disabled by programming bit 3 in the SX1 Control Register (see Table 13) to logic 0.
Transmit Section
To minimize the post-PA filtering requirements and any additional post-PA losses, the transmit path consists of a vector modulator within a frequency translation loop. The translation loop consists of the following: * * * * * Phase Frequency Detector (PFD) and charge pump Mixer with an operating range of 800 MHz to 2 GHz An in-loop modulator Two programmable dividers Two transmit VCOs
Translational Loop The translational loop takes baseband analog I/Q signals and modulates them with the mixed product of transmitter output and LO signal, as shown in Figure 6. The unmodulated result is compared with a divided down LO at the PFD and the difference is used to control the transmit VCO. The on-chip Low Pass Filter (LPF) following the mixer attenuates the unwanted sidebands as well as harmonics. Transmit VCOs Two on-chip transmit VCOs are designed to meet GSM850, EGSM900, DCS1800, and PCS1900 requirements. The transmit VCOs use the same DFC technique as described in the Synthesizer section to lock the translational loop. The rising edge on TXENA initializes the transmit DFC.
XTALTUNE (Pin 39) VCXO_EN (Pin 4) XTAL (Pin 34)
CAP_B CAP_A
PLL
/2
VCCF (Pin 33) Baseband Buffer [SX Register 1 (bit 3)] BUF_EN XTAL_BUF (Pin 30) to baseband
C1337
Figure 7. VCXO Block Diagram
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Data Sheet I CX74063-34/-35/-36
Coupler
PA
Register 4 VCC2
8
PAC Delay Timer
TXENA (pin 2)
PAVAPC (pin 16)
+ -
Power Detector
PDETVCC (pin 5) PDET (pin 12)
5 pF
10 k
from baseband
BBVAPC (pin 17)
Bias Generator
1
Rx/Tx Control Register (bit 21), PDETVCC
0 = 0.5 V 1 = 1.0 V C1338a
Figure 8. PA Controller Block Diagram
Power Amplifier Gain Controller The device contains an error amplifier/integrator to provide transmit burst control for an external power amplifier (PA). As shown in Figure 8, when the device is connected to a PA, an RF detector, and a coupler, a loop is formed that controls the transmit power in a multi-band wireless application. The error amplifier amplifies and integrates the voltage difference between the RF detector output (PDET) and the power control input (BBVAPC). The output of the integrator is fed to an internal gain shaper that drives the gain control input (PAVAPC) of the external RF PA. The device. provides a bandgap voltage (PDETVCC) which can be used as the supply voltage for the external peak detector and can source up to 200 A. The PA pre-bias is activated after a programmable delay and time-referenced from the rising edge of TXENA. The time delay is set using the serial interface. See Table 19 for details.
The RX/TX Control Register is used to program the transceiver and to preset other test word states by setting bit 22 as a logic 1. If any test words are to be altered from their preset states, bit 22 must be sent to the RX/TX Control Register again as a logic 0. Typically, this is done only on power-up since the device has a zero-power standby mode that retains programmed test memory. There are eight additional registers used to program various functions of the CX74063-3x. The SX1 Control Register is used to program the fractional-N synthesizer and the SX2 Fractional-N Modulo Register is used to program the modulus. Four auxiliary registers are used to program the transceiver besides the RX/TX Control Register, and two 24-bit registers are used to program the synthesizer: * * * * * * * * * SX1 Synthesizer Control SX2 Fractional-N Modulo RX/TX Control R0 Auxiliary Control R2 DC Offset Timing R3 IP2 Calibration R4 PAC Timing Control R6 VCXO Control R7 VCXO Control
Digital Interface
The transceiver and synthesizer are controlled by a single three-wire serial interface. The transmitter, receiver, and synthesizer are each enabled through external inputs according to typical timing requirements as shown in Figures 10 and 11. Band selection for the CX74063-3x is through the three-wire serial interface. The PCO signal (pin 3) provides a band selection control output. DC offset calibration and front-end activation timing can also be controlled by an on-chip signal sequencer, precluding the need for separate control signals. All the logic and the three-wire interface inputs are referenced to the PCO signal (pin 3). 14
NOVEMBER 25, 2003
SX1 Control Register. This register is used to program the fractional-N synthesizer, and set the values of the integral-N divider and the input-R divider. The polarity of the Phase/Frequency Detector (PFD) may also be defined by this register. Refer to Table 13.
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Data Sheet I CX74063-34/-35/-36 SX2 Fractional-N Modulo Register. This register is used to program the 24-bit modulo of the fractional-N synthesizer. The data is a 22-bit binary coded decimal word that allows the PLL to lock to precise frequencies. Refer to Table 14. RX/TX Control Register. This register is used to control divide ratios and charge pump currents in the transmitter, and to control gain in the receiver along with the band select function. Refer to Table 15. R0 Auxiliary Control Register. This register is used to bypass the DC offset correction loops and the baseband filters. It also enables and disables the two on-chip transmit VCOs and defines the directionality of the LO port, which allows an external VCO or LO reference to be used or enables the internal VCO to be monitored. Refer to Table 16. R2 DC Offset Timing Register. This register sets the timing of the tracking of the three DC offset cancellation loops and the time at which the front end turns on relative to the RXENA signal (pin 1). It allows the front-end to be enabled using the internal timer. Refer to Table 17. R3 IP2 Calibration Register. This register is used to perform 2nd order Intercept Point (IP2) calibration by manually adjusting calibration coefficients. A total of four words need to be set: IP2 coefficients for I-high band, I-low band, Q-high band, and Q-low band. Refer to Table 18. The IP2 coefficient is eight bits long (including polarity) and is intended to be a factory calibration. An algorithm using a test tone needs to be used to determine the coefficient for each individual part. R4 PAC Timing Control Register. This register is used to set timing for the PAC pedestal. Refer to Table 19. R6 and R7 VCXO Control Registers. These registers are used to control the tuning range and oscillation frequency of the VCXO. See Tables 20 and 21, respectively.
Package and Handling Information
Because this device package is sensitive to moisture absorption, it is baked and vacuum packed before shipment according to IPC J-STD 033 guidelines. Instructions on the shipping container label regarding exposure to moisture after the container seal is broken must be followed. These instructions adhere to IPC J-STD 020A guidelines for handling moisture sensitive devices. If these instructions are not followed, problems related to moisture absorption may occur when the part is subjected to high temperature during solder assembly. The CX74063-3x transceiver is available in both low temperature and high temperature attachment packages. The RFLGA package for the low temperature attachment option provides a circular-shaped ground pad (CX74063-34). The RFLGA package for the high temperature options is available with both a circular-shaped ground pad and a four-quadrant, split center ground pad (CX74063-35 and CX74063-36, respectively). Refer to Figures 28 and 29 for package dimensions. Guidelines for CX74063-3x low and high temperature attachment techniques are provided below. For additional details on attachment techniques, precautions, and recommended handling procedures, refer to the Skyworks' Application Note, PCB Design & SMT Assembly Guidelines for RFLGA Packages, document number 103147. For The -34 Low Temperature Package Option: If the CX74063-34 is attached in a reflow oven, the temperature ramp rate should not exceed 3 C per second. Maximum temperature should not exceed 240 C and the time spent at a temperature that exceeds 235 C should be limited to less than 10 seconds. If the part is manually attached, precaution should be taken to ensure that the part is not subjected beyond a maximum temperature of 240 C or exceeds 235 C for more than 10 seconds. Care must be taken when this product is attached, whether it is done manually or in a production solder reflow environment, to NOT heat the part beyond the recommended temperature. Measure the temperature on the package itself by attaching thermocouples to the package body. For The -35 and -36 High Temperature Package Options: If the CX74063-35 or the CX74063-36 are attached in a reflow oven, the temperature ramp rate should not exceed 3 C per second. Maximum temperature should not exceed 260 C and the time spent at a temperature that exceeds 255 C should be limited to less than 15 seconds.
Electrical and Mechanical Specifications
The absolute maximum ratings of the CX74063-3x are provided in Table 3. The recommended operating conditions are specified in Table 4. Electrical specifications are provided in Tables 5 through 11. Tables 12 through 21, and Figures 9 through 11 provide the serial interface programming states, functions, and timing curves. Receiver data is shown in Tables 22 through 33 and illustrated in Figures 12 through 20. Transmit data is illustrated in Figures 21 through 26. A typical application circuit using the CX74063-3x is shown in Figure 27. The 56-pin RFLGA package dimensions are provided in Figure 28 (-34 and -35 package options) and Figure 29 (-36 package option). Tape and reel dimensions are shown in Figure 30 (-34 and -36 package options) and Figure 31 (-35 package option). Typical package case markings are explained in Figure 32.
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Data Sheet I CX74063-34/-35/-36 If the part is manually attached, precaution should be taken to ensure that the part is not subjected beyond a maximum temperature of 260 C or exceeds 255 C for more than 15 seconds. Care must be taken when this product is attached, whether it is done manually or in a production solder reflow environment, to NOT heat the part beyond the recommended temperature. Measure the temperature on the package itself by attaching thermocouples to the package body. Production quantities of this product are shipped in a standard tape and reel format. For packaging details, refer to the Skyworks' Application Note, Tape and Reel, document number 101568. Typical case markings for the CX74063-3x are shown in Figure 31.
Electrostatic Discharge
The CX74063-3x contains Class 1 devices. The following Electrostatic Discharge (ESD) precautions are recommended: * * * * * Protective outer garments Handle device in ESD safeguarded work area Transport device in ESD shielded containers Monitor and test all ESD protection equipment Treat the CX74063-3x as extremely sensitive to ESD
Table 3. CX74063-3x Absolute Maximum Ratings
Parameter
Supply voltage (VCC) Ambient operating temperature range Storage temperature range Input voltage range Maximum power dissipation
Minimum
-0.3 -40 -50 GND
Maximum
+3.6 +95 +125 VCC 600
Units
V C C V mW
Note: Stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to maximum rating conditions for extended periods may reduce device reliability.
Table 4. CX74063-3x Recommended Operating Conditions
Parameter
LNA input level (pins 9, 11, 13) RXEN = Off Power supply Digital power supply, VDDBB Operating junction temperature Operating ambient temperature
Minimum
Typical
Maximum
10
Units
dBm V V C C
2.6 1.8 -40 -30
2.8
3.3 3.3 +110 +85
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Data Sheet I CX74063-34/-35/-36
Table 5. Power Consumption Specifications (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Total supply current: Rx section, EGSM/GSM850 Tx section, EGSM/GSM850 (includes TX VCO) Synthesizer section, EGSM/GSM850 (includes UHF VCO) Rx section, DCS/PCS Tx section, DCS/PCS (includes TX VCO) Synthesizer section, DCS/PCS (includes UHF VCO) Sleep mode
Symbol
ICC
Test Condition
Min
Typical
Max
Units
RXENA=H; SXENA=L TXENA=H; SXENA=L SXENA=H RXENA=H; SXENA=L TXENA=H; SXENA=L SXENA=H @ VCC = 3.3 V RXENA=L; TXENA=L; SXENA=L
41 121 39 49 126 39 20
48 137 46 58 143 46 100
mA mA mA mA mA mA A
Table 6. CX74063-3x Electrical Specifications - EGSM/GSM850 Receiver (1 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Input impedance. See Figure 12 for unmatched input impedance. Input operating frequency Receiver maximum voltage gain Receiver minimum voltage gain Receiver gain temperature variation Gain step Gain step accuracy
Symbol
ZIN Band 1 GRXMAX GRXMIN GTEMVAR AV GSTEP
Test Condition (Note 1)
With external match
Min
Typical
50
Max
Units

869 Highest gain mode Lowest gain mode TA = -30 C to +85 C 2 Over range recommended in Table 25 Over 869-894 MHz Over 925-960 MHz -0.75 120 126 11
960
MHz dB
17 4.5
dB dB dB
+0.75
dB
Gain variation versus frequency
GFREQ
2 2 3.2 3.9 5.0 5.2
dB dB dB dB dB
Noise Figure Noise Figure (temperature)
NFGAIN1 NFTEMP
G = 15/40/10/12/0/18 TA = +75 C TA = +85 C G = 15/40/10/12/0/18
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Data Sheet I CX74063-34/-35/-36
Table 6. CX74063-3x Electrical Specifications - EGSM/GSM850 Receiver (2 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Noise Figure degradation in presence of blocker
Symbol
NFBLOC
Test Condition (Note 1)
With -26 dBm input blocker @ 3 MHz offset (ideal LO) Internal LO G = 15/40/10/12/0/18
Min
Typical
2
Max
Units
dB
4
dB
Input 2nd order intercept point
IIP2
Referred to LNA input calibrated and measured at middle of EGSM or GSM850 band. With -34 dBm @ 6 MHz offset G = 15/40/10/12/0/18 @ wanted frequency @ 3 MHz offset @ 1.6 MHz offset @ 600 kHz offset @ 400 kHz offset @ 200 kHz offset TA = -30 C to +85 C
50
65
dBm
DC shift in presence of blocker
AM Supp
17
mV
LO re-radiation @ LNA input Selectivity
LOREV
-110 143 128 61 37 9 137 68 44 13
-100
dBm dB dB dB dB dB
I/Q amplitude imbalance I/Q phase imbalance Input 1 dB compression point IP1dB
TA = -30 C to +85 C TA = -30 C to +85 C F = 200 kHz, G = 15/40/-2/8/0/18 F = 400 kHz, G = 15/40/-2/8/0/18 F = 600 kHz, G = 15/40/10/12/0/18 F = 1.6 MHz, G = 15/40/10/12/0/18 F = 3.0 MHz, G = 15/40/10/12/0/18 -3 -65 -45 -35 -32 -25 -15 -15 -60 -40 -30 -28 -22 -12 -12
1 +3
dB degrees dBm dBm dBm dBm dBm dBm dBm
3rd order intercept point @ +25 C 3rd order intercept point @ -20 C
IIP3 IIP3
F = 3.0 MHz G = 15/40/10/12/0/18 F = 3.0 MHz G = 15/40/10/12/0/18
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Data Sheet I CX74063-34/-35/-36
Table 6. CX74063-3x Electrical Specifications - EGSM/GSM850 Receiver (3 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Output offset voltage
Symbol
Test Condition (Note 1)
With DC offset corrected while LNA is off TA = +85C With DC offset corrected while LNA is on G=15/40/10/12/0/18 TA = +85 C (60 s total DC correction time)
Min
Typical
Max
200
Units
mV
220 20
mV mV
25
mV
Offset drift (long term) Offset drift (short term)
DCDRFT1 DCDRFT2
50 ms after correction G = 15/40/10/12/0/18 577 s after correction G = 15/40/10/12/0/18 Baseband Tunable Active Filter
100 10
mV mV
3 dB corner frequency (tunable) Corner frequency variation
FC dFC 39.2 k at pin 29 470 pF at pins 25-26 and 27-28 Receiver Output Stage
80 -11
100 +11
kHz %
Differential output amplitude (pk/pk differential) Output common mode voltage Maximum current drive Output resistance IOUT ROUT
VGA2 = 30 dB VGA2 = 0 dB TA = -30 C to +85 C
3.7 0.3 VCC/2 - 0.1 VCC/2 VCC/2 + 0.1 0.5
V V V mA    pF
RXENA = H, RXENA = L, differential RXENA = L, singleended
160 >1M
200 40k
240
Output capacitance
COUT
1
Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.
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Data Sheet I CX74063-34/-35/-36
Table 7. CX74063-3x Electrical Specifications - DCS1800 Receiver (1 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Input impedance See Figure 13 for unmatched input impedance. Input operating frequency Receiver maximum voltage gain Receiver minimum voltage gain Gain step Receiver gain temperature variation Gain step accuracy
Symbol
ZIN Band 2 GRXMAX GRXMIN AV GTEMPVAR GSTEP
Test Condition (Note 1)
With external match DCS Rx band Highest gain mode Lowest gain mode
Min
Typical
50
Max
Units

1805 117 123 9 2
1880
MHz dB
15
dB dB
TA = -30 C to +85 C Over range recommended in Table 26 Over band 2 G = 15/40/10/12/0/18 TA = +75 C TA = +85 C With -30 dBm input blocker @ 3 MHz offset (ideal LO) Internal LO G = 15/40/10/12/0/18 2 3.6 -0.75
4.5 +0.75
dB dB
Gain variation versus frequency Noise Figure Noise Figure (temperature) Noise Figure degradation in presence of blocker
GFREQ NFGAIN1 NFTEMP NFBLOC
2 4.3 5.4 5.6
dB dB dB dB
4
dB
Input 2nd order intercept point
IIP2
Referred to LNA input calibrated and measured at middle of DCS1800 band. With -33 dBm @ 6 MHz offset G = 15/40/10/12/0/18 @ wanted frequency @ 3 MHz offset @ 1.6 MHz offset @ 600 kHz offset @ 400 kHz offset @ 200 kHz offset TA = -30 C to +85 C
50
65
dBm
DC shift in presence of blocker
AM Supp
17
mV
LO re-radiation @ LNA input Selectivity
LOREV
-110 143 128 61 37 9 137 68 41 13
-100
dBm dB dB dB dB dB
I/Q amplitude imbalance I/Q phase imbalance
TA = -30 C to +85 C TA = -30 C to +85 C -3
1 +3
dB degrees
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Data Sheet I CX74063-34/-35/-36
Table 7. CX74063-3x Electrical Specifications - DCS1800 Receiver (2 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Input 1 dB compression point
Symbol
IP1dB
Test Condition (Note 1)
F = 200 kHz, G = 15/40/-2/8/0/18 F = 400 kHz, G = 15/40/-2/8/0/18 F = 600 kHz, G = 15/40/10/12/0/18 F = 1.6 MHz, G = 15/40/10/12/0/18 F = 3.0 MHz, G = 15/40/10/12/0/18
Min
-65 -45 -35 -32 -25 -15 -15
Typical
-60 -40 -30 -28 -22 -12 -12
Max
Units
dBm dBm dBm dBm dBm dBm dBm
3rd order intercept point @ +25 C 3rd order intercept point @ -20 C Output offset voltage
IIP3 IIP3
F = 3.0 MHz G = 15/40/10/12/0/18 F = 3.0 MHz G = 15/40/10/12/0/18 With DC offset corrected while LNA is off TA = + 85C With DC offset corrected while LNA is on G = 15/40/10/12/0/18 TA = + 85 C (60 s total DC correction time)
200
mV
220 20
mV mV
25
mV
Offset drift (long term) Offset drift (short term)
DCDRFT1 DCDRFT2
G = 15/40/10/12/0/18 50 ms after correction G = 15/40/10/12/0/18 577 s after correction Baseband Tunable Active Filter
100 10
mV mV
3 dB corner frequency (tunable) Corner frequency variation
FC dFC 39.2 k at pin 29 470 pF at pins 25-26 and 27-28
80 - 11
100 + 11
kHz %
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Data Sheet I CX74063-34/-35/-36
Table 7. CX74063-3x Electrical Specifications - DCS1800 Receiver (3 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition (Note 1)
Receiver Output Stage
Min
Typical
Max
Units
Differential output amplitude (pk/pk differential) Output common mode voltage Maximum current drive Output Resistance IOUT ROUT
VGA2 = 30 dB VGA2 = 0 dB
3.7 0.3 VCC/2 - 0.1 VCC/2 VCC/2 + 0.1 0.5
V V V mA    pF
RXENA = H, RXENA = L, differential, RXENA = L, singleended
160 >1M
200 40k
240
Output Capacitance
COUT
1
Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.
Table 8. CX74063-3x Electrical Specifications - PCS1900 Receiver (1 of 3) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Input impedance. See Figure 14 for unmatched input impedance. Input operating frequency Receiver maximum voltage gain Receiver minimum voltage gain Receiver gain temperature variation Gain step Gain step accuracy
Symbol
ZIN Band 3 GRXMAX GRXMIN GTEMPVAR AV GSTEP
Test Condition (Note 1)
With external match PCS Rx band Highest gain mode Lowest gain mode TA = -30 C to +85 C
Min
Typical
50
Max
Units

1930 117 123 7
1990
MHz dB
13 4.5
dB dB dB
2 Over range recommended in Table 27 Over band 3 G = 15/40/10/14/0/18 TA = +75 C TA = +85 C With -30 dBm input blocker @ 3MHz offset (ideal LO) Internal LO G = 15/40/10/14/0/18 2 4.2 -0.75 +0.75
dB
Gain variation versus frequency Noise Figure Noise Figure (temperature) Noise Figure degradation in presence of blocker
GFREQ NFGAIN1 NFTEMP NFBLOC
2 4.9 6.0 6.2
dB dB dB dB
4
dB
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Data Sheet I CX74063-34/-35/-36
Table 8. CX74063-3x Electrical Specifications - PCS1900 Receiver (2 of 3) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Input 2nd order intercept point
Symbol
IIP2
Test Condition (Note 1)
Referred to LNA input calibrated and measured at middle of PCS1900 band With -33 dBm @ 6 MHz offset G = 15/40/10/14/0/18 @ wanted frequency @ 3 MHz offset @ 1.6 MHz offset @ 600 kHz offset @ 400 kHz offset @ 200 kHz offset TA = -30 C to +85 C
Min
50
Typical
65
Max
Units
dBm
DC shift in presence of blocker
AM Supp
17
mV
LO Re-radiation @ LNA input Selectivity
LOREV
-110 143 128 61 37 9 137 68 41 13
-100
dBm dB dB dB dB dB
I/Q amplitude imbalance I/Q phase imbalance Input 1 dB compression point IP1dB
TA = -30 C to +85 C TA = -30 C to +85 C F = 200 kHz, G = 15/40/-2/8/0/18 F = 400 kHz, G = 15/40/-2/8/0/18 F = 600 kHz, G = 15/40/10/14/0/18 F = 1.6 MHz, G = 15/40/10/14/0/18 F = 3.0 MHz, G = 15/40/10/14/0/18 -3 -65 -45 -35 -32 -25 -15 -15 -60 -40 -30 -28 -22 -12 -12
1 +3
dB degrees dBm dBm dBm dBm dBm dBm dBm
3rd order intercept point @ +25 C 3rd order intercept point @ -20 C Output offset voltage
IIP3 IIP3
F = 3.0 MHz G = 15/40/10/14/0/18 F = 3.0 MHz G = 15/40/10/14/0/18 With DC offset corrected while LNA is off TA = +85C With DC offset corrected while LNA is on TA = +85 C G = 15/40/10/12/0/18 (60 s total DC correction time)
200
mV
220 20
mV mV
25
mV
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Data Sheet I CX74063-34/-35/-36
Table 8. CX74063-3x Electrical Specifications - PCS1900 Receiver (3 of 3) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Offset drift (long term) Offset drift (short term)
Symbol
DCDRFT1 DCDRFT2
Test Condition (Note 1)
50 ms after correction G = 15/40/10/14/0/18 577 s after correction G = 15/40/10/14/0/18 Baseband Tunable Active Filter
Min
Typical
Max
100 10
Units
mV mV
3 dB corner frequency (tunable) Corner frequency variation
FC dFC 39.2 k at pin 29 470 pF at pins 25-26 and 27-28 Receiver Output Stage
80 -11
100 +11
kHz %
Differential output amplitude (pk/pk differential) Output common mode voltage Maximum current drive Output resistance IOUT ROUT
VGA2 = 30 dB VGA2 = 0 dB
3.7 0.3 VCC/2 - 0.1 VCC/2 VCC/2 + 0.1 0.5
V V V mA    pF
RXENA = H, RXENA = L, differential, RXENA = L, singleended
160 >1M
200 40k
240
Output capacitance
COUT
1
Note 1: Gain codes refer to LNA/Mixer/LPF1/VGA1/AUX/VGA2 gains in dB.
Table 9. CX74063-3x Electrical Specifications - Transmitter (1 of 4) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
I/Q Modulator
Min
Typical
Max
Units
  
Input impedance
ZIN
TXENA = H, differential, TXENA = L, differential, TXENA = L, singleended Differential
400k 60k >1M 0.8 0.85 1 1.35 3 1.2 VCC - 1.3
Input signal level Input common mode voltage range Input frequency 3 dB bandwidth Input common mode rejection ratio VCM
Vp-p V MHz dB
fIN = 100 kHz fIN = 1 MHz
65 45 70
75 55 130 200 -33 230
Output operating frequency Output impedance Output voltage
FOUT ZOUT VOUT Per side
MHz  dBV
170
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Data Sheet I CX74063-34/-35/-36
Table 9. CX74063-3x Electrical Specifications - Transmitter (2 of 4) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
I/Q Modulator (continued)
Min
Typical
Max
Units
Output noise power
NO
@ 10 MHz offset @ 1.8 MHz offset
-132 -130 30 30 35 35
-128 -126
dBc/Hz dBc/Hz dBc dBc
LO suppression Sideband suppression Translational Loop Spurious Modulation 2nd order Modulation 3rd order Transmit frequency (input from VCO) IF frequency Transmit input power Transmit input impedance Transmitter output phase noise (includes TX VCO and LO PLL) FTX FIF PIN ZIN NO @ 400 kHz offset @ 1.8 MHz offset @ 10 MHz offset EGSM/GSM850 @ 20 MHz offset EGSM/GSM850 @ 20 MHz offset DCS/PCS Tx phase error TxPHERR rms (employs reference frequency source, and loop filters as shown in the reference design) RX/TX Control Register bits S17 S16 CP = 0 0 CP = 0 1 CP = 1 0 CP = 1 1 0.3  VCPO  VCC - 0.5 0.3  VCPO  VCC - 0.5 TA = -30 C to +85 C With external 50  termination
-70 -60 800 70 -20 -15 300// 0.3 -120 -130 -152 -164 -156 2.0
-40 -55 2000 130 -10
dBc dBc MHz MHz dBm // pF
-118 -124 -150 -162 -154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz degrees
Charge pump output current: high impedance source/sink
IOUT
0.5 0.75 1.0 1.25 20 10 9 1 12 2 -60
mA mA mA mA % %
Charge pump current variation Charge pump current variation over temperature D1 divide ratio range D2 divide ratio Tx mixer LO leakage TXMIX LEAKAGE
Tx mixer 50  terminated
dBm
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Data Sheet I CX74063-34/-35/-36
Table 9. CX74063-3x Electrical Specifications - Transmitter (3 of 4) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Low Band Translation Loop VCO Center frequency Digital frequency centering resolution Digital frequency centering time fC eDFC tDFC From rising edge of TXENA (13 MHz clock frequency) Control voltage at end of DFC/start of analog lock 0.5 < VCTL < 2.2 (0.9 V < VCTL and 1.9 V > VCTL) 820 MHz < fC < 850 MHz 870 MHz < fC < 915 MHz Output harmonics 2nd harmonic 3rd harmonic Phase noise @ 400 kHz offset @ 20 MHz offset Output VSWR Pushing Pulling Output power Output power temperature variation POUT VSWR 2:1 FOUT = 897.5 MHz with external 50  match TA = -30C to +85C High Band Translation Loop VCO Center frequency Digital frequency centering resolution Digital frequency centering time fC eDFC tDFC From rising edge of TXENA (13 MHz clock frequency) Control voltage at end of DFC/start of analog lock VCC/2 - 0.2 TA = -30 C to +85 C 1700 6 12 20 1930 MHz MHz s 10.5 11.5 0.7 With external 50  match 2 16 18 21 25 -50 - 55 -125 -164 26 32 -30 -30 -120 -162 2:1 4 4 12.5 MHz/V MHz dBm dB MHz/V MHz/V dBc dBc dBc/Hz dBc/Hz VCC/2 - 0.2 TA = -30 C to +85 C 800 2.5 12 20 930 MHz MHz s
Digital frequency centering voltage
VDFC
VCC/2
VCC/2 + 0.2
V
Analog frequency control range Absolute control sensitivity
fMAX - fMIN KVCO
20
MHz
Digital frequency centering voltage
VDFC
VCC/2
VCC/2 + 0.2
V
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Table 9. CX74063-3x Electrical Specifications - Transmitter (4 of 4) (TA =2 5 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
High Band Translation Loop VCO (continued) Analog frequency control range Absolute control sensitivity fMAX - fMIN KVCO 0.5 < VCTL < 2.2 1710 MHz < fC < 1785 MHz 1850 MHz < fC < 1910 MHz 0.9 V < VCTL and 1.9 V > VCTL Output harmonics 2nd harmonic 3rd harmonic Phase noise @ 400 kHz offset @ 20 MHz offset Output VSWR Pushing Pulling Output power Output power variation POUT VSWR 2:1 Fout = 1747.5 MHz with external 50  match TA = -30 C to +85 C PA Gain Controller PAVAPC output swing PAVAPC offset voltage PAVAPC sink current PAVAPC source current Open loop gain Input common mode range PDETVCC source current PDETVCC output voltage IPDETVCC PDETVCC = 0 (bit 21 of RX/TX Control Register) PDETVCC = 1 (bit 21 of RX/TX Control Register) Output load ISINK ISOURCE G 104 0 200 0.5 1.0 10pF // 10k TXENA = H 0.22 0.68 550 750 111 2.7 VCC - 0.3 V V A A dB V A V V 5.5 7 1 with external 50  match 2 -50 -55 -125 -158 -30 -30 -120 -155 2:1 4 4 8.5 MHz/V MHz dBm dB dBc dBc dBc/Hz dBc/Hz 20 14 19 18 23 22 27 MHz MHz/V MHz/V
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Data Sheet I CX74063-34/-35/-36
Table 10. CX74063-3x Electrical Specifications - Synthesizer (1 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Prescaler operating input frequency Reference input frequency Phase detector frequency External crystal oscillator input sensitivity Reference oscillator sensitivity In-band phase noise Charge pump output current (can be programmed in four steps)
Symbol
Test Condition
Min
1000 10
Typical
Max
1700
Units
MHz MHz MHz dBm VPEAK dBc/Hz A
13 13
26 15 +3 VCC
-15 0.4 Measured within the loop bandwidth VCP = VCCFN_CP/2 (SX1 Control Register, bit[6:5] = 00) VCP = VCCFN_CP/2 (SX1 Control Register, bit[6:5] = 01) VCP = VCCFN_CP/2 (SX1 Control Register, bit[6:5] = 10) VCP = VCCFN_CP/2 (SX1 Control Register, bit[6:5] = 11) -85 100
200
A
300
A
400
A
Charge pump leakage current Charge pump sink versus source mismatch Charge pump current versus voltage Charge pump current versus temperature
0.5 < VCP < VCCFN_CP - 0.5 VCP = VCCFN_CP/2 0.5 < VCP < VCCFN_CP - 0.5 VCP = VCCFN_CP/2 TA = -30C to +85C UHF VCO
0.1 5 10 10
nA % % %
Center frequency Digital frequency centering resolution Digital frequency centering time
fC eDFC tDFC
TA = -30 C to +85 C
1200 2
1550
MHz MHz
From rising edge of SXENA or LE when programming SX word (13 MHz clock frequency) Control voltage at end of DFC/start of analog lock 0.5 < VCTL < 2.2 VCCUHF/2 - 0.2 30
12
20
s
Digital frequency centering voltage
VDFC
VCCUHF/2
VCCUHF/2 + 0.2
V
Analog frequency control range
fMAX - fMIN
MHz
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Table 10. CX74063-3x Electrical Specifications - Synthesizer (2 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
UHF VCO (continued)
Min
Typical
Max
Units
Relative control sensitivity
KVCO/fC
After DFC, within the range of eVCTL 1200 MHz < fC < 1300 MHz 1300 MHz < fC < 1400 MHz 1400 MHz < fC < 1475 MHz 1475 MHz < fC < 1550 MHz 1.3 1.5 1.7 1.9 1.7 2.0 2.2 2.4 2.1 2.4 2.6 2.8 %/V %/V %/V %/V
Absolute control sensitivity
KVCO
VDCF + eVCTL,MIN < VCTL and VDCF + eVCTL,MAX > VCTL 1200 MHz < fC < 1300 MHz 1300 MHz < fC < 1400 MHz 1400 MHz < fC < 1475 MHz 1475 MHz < fC < 1550 MHz 15 19 24 28 21 27 32 36 -123 -140 -5 28 34 39 44 -121 -137 +5 MHz/V MHz/V MHz/V MHz/V dBc/Hz dBc/Hz MHz/sec
Phase noise
@ 400 kHz offset @ 3 MHz offset
Slow center frequency drift
fC/t
TA = -30C to + 85C 26 MHz Crystal Oscillator
Operating frequency Buffer output frequency Phase noise: @ 100 Hz @ 1 kHz @ 10 kHz Clock jitter Spurious rejection Digital tuning (Note 1) Analog tuning (Note 1) Analog varactor voltage range Analog varactor DC impedance VTUNE = 0.05 to 2.5 V 0 45
26 13 -98 -127 -145 16 -20 70 23 VCC 1 -15
MHz MHz dBc/Hz dBc/Hz dBc/Hz ps dBc ppm ppm V M
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Data Sheet I CX74063-34/-35/-36
Table 10. CX74063-3x Electrical Specifications - Synthesizer (3 of 3) (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Symbol
Test Condition
2.8  0.1 V
Min
Typical
Max
Units
26 MHz Crystal Oscillator (continued) Supply voltage dependence Operating current (start) @ 26 MHz Operating current (equilibrium) @ 26 MHz Voltage swing @ crystal Voltage swing @ buffer Buffer output load Start-up time Note 1: Using a crystal with equivalent 6 mH inductor and ESR  100 . 1 2600 2600 1.1 1.1 10pF || 10 k 4 ms 2 ppm/V A A Vpp Vpp
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Data Sheet I CX74063-34/-35/-36
Table 11. CX74063-3x Electrical Specifications - Digital Interface (TA = 25 C, VCC = 2.8 V unless otherwise noted)
Parameter
Data to clock setup time (Note 1) Data to clock hold time (Note 1) Clock pulse width high (Note 1) Clock pulse width low (Note 1) Clock to load enable setup time (Note 1) Load enable pulse width (Note 1) LE falling edge to clock rising edge (Note 1) RXENA setup time TXENA setup time SXENA setup time High level input voltage for RXENA, TXENA, DATA, CLK, LE, PCO, VCXO_EN, and SXENA Low level input voltage for RXENA, TXENA, DATA, CLK, LE, PCO, VCXO_EN, and SXENA High level input current for RXENA, TXENA, DATA, CLK, LE, PCO, VCXO_EN, and SXENA Low level input current for RXENA, TXENA, DATA, CLK, LE, PCO, VCXO_EN, and SXENA Digital input pin capacitance for RXENA, TXENA, DATA, CLK, LE, PCO, VCXO_EN, and SXENA High level output voltage for PCO Low level output voltage for PCO Digital output pin load capacitance for PCO Note 1: See Figure 9.
Symbol
TCS TCH TCWH TCWL TES TEW TEFC
Test Condition
Min
30 10 30 30 30 50 30 30 30 30
Typical
Max
Units
ns ns ns ns ns ns ns ns ns ns V
VIH
0.8 x VDDBB 0.2 x VDDBB -1 +1
VIL
V
IIH
A
IIL
-1
+1
A
CID
10
pF
VOH VOL CLD
IOH = -1.0 mA IOL = 1.0 mA
VDDBB - 0.4 0.4 15
V V pF
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Data Sheet I CX74063-34/-35/-36
Serial Interface Programming
Table 12. Control and Output States
Register B6
SX Register 1: Synthesizer Control SX Register 2: Fractional-N Modulo RX/TX Control Register R0: Auxiliary Control R2: DC Offset Timing R3: IP2 Calibration R4: PAC Timing Control R6: VCXO Control R7: VCXO Control X X X X X X X 0 1
Address Bits B5
X X X X X 0 0 1 1
B4
X X X X X 0 1 0 0
B3
X X X 0 1 1 1 1 1
B2
X X X 0 0 1 1 1 1
B1
0 1 1 0 0 0 0 0 0
B0
0 0 1 1 1 1 1 1 1
Table 13. SX Register 1: Synthesizer Control Functions
Symbol
ADDR EN BUF_EN SP SC
Function
Address bits [1:0]. Must be set to 00b (see Table 12) Enable mode [2] Buffer enable [3] Phase detector output polarity [4] Charge pump output current [6:5]
State Description
0 enables synthesizer 1 disables synthesizer 0 sets buffer to off state 1 sets buffer to on state 0 sets phase detector output for negative VCO gain 1 sets phase detector output for positive VCO gain Bit [6:5] 0 0 sets charge pump current to 100 A 0 1 sets charge pump current to 200 A 1 0 sets charge pump current to 300 A 1 1 sets charge pump current to 400 A
RSVD N R
Reserved Main divider [19:9] Reference divider [23:20]
Bit [8:7]: set bit 8 = 1, bit 7 = 0 Sets 11-bit main divider ratio range (64...2047) Sets 4-bit reference divider ratio range (1...15)
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Table 14. SX Register 2: Fractional-N Modulo
Symbol
ADDR FN
Function
Address bits [1:0]. Must be set to 10b (see Table 12) Fractional-N modulo [23:2]
State Description
Sets fractional-N modulo up to 222 range (0...4,194,303)
Table 15. RX/TX Control Register (1 of 2)
Symbol
ADDR LNA MIX LPF1 VGA2
Function
Address bits [1:0]. Must be set to 11b (see Table 12) LNA gain step control [2] Mixer gain step [3] 1st LPF gain step [4] VGA2 gain steps [7:5]
State Description
0 selects low gain mode of LNA 1 selects high gain mode of LNA 0 selects low gain mode of RX mixer 1 selects high gain mode of RX mixer 0 selects low gain mode of the first active LPF 1 selects high gain mode of the first active LPF Bit 7 to bit 5 program the VGA2 gain in 6 dB increments Bit 7, Bit 6, Bit 5 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 sets the gain to 30 dB sets the gain to 24 dB sets the gain to 18 dB sets the gain to 12 dB sets the gain to 6 dB sets the gain to 0 dB not used not used
AUX VGA1
Auxiliary gain [8] VGA1 gain steps [11:9]
0 sets 0 dB auxiliary gain post gmC filter 1 sets 6 dB auxiliary gain post gmC filter Bit 11 to bit 9 program the VGA1 gain in the following increments: Bit 11, Bit 10, Bit 9 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 sets the gain to 0 dB sets the gain to 24 dB sets the gain to 12 dB not used sets the gain to 6 dB sets the gain to 30 dB sets the gain to 18 dB not used
VGA1FINE
VGA1 fine gain step [13:12]
Bit 13 and bit 12 program VGA1 in 2 dB increments Bit 13, Bit 12 0 0 1 1 0 1 0 1 sets gain to 0 dB sets gain to 4 dB sets gain to 2 dB not used
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Data Sheet I CX74063-34/-35/-36
Table 15. RX/TX Control Register (2 of 2)
Symbol
SOFTSEL
Function
Software band select [15:14] Bit 15, Bit 14 0 0 1 1 0 1 0 1
State Description
not used selects EGSM/GSM850, PCO = 0 selects DCS, PCO = 1 selects PCS, PCO = 1
TXCP
TX charge pump bits [17:16]
Translational loop charge pump current setting Bit 17, Bit 16 0 0 1 1 0 1 0 1 sets TXCP to 0.5 mA sets TXCP to 0.75 mA sets TXCP to 1.0 mA sets TXCP to 1.25 mA
TXD1
TX divider D1 [19:18]
Translational loop D1 divider setting Bit 19, Bit 18 0 0 1 1 0 1 0 1 sets D1 to 9 sets D1 to 11 sets D1 to 10 sets D1 to 12
TXD2
TX divider D2 [20]
Translational loop D2 divider setting: 0 sets D2 to 1 1 sets D2 to 2 Bit [21] sets bias voltage for the Schottky diode pair: 0 = 0.5 V 1 = 1.0 V 0 allows changing contents of R0 to R7 1 allows loading default words into R0 to R7 Upon power up, program RX/TX control register with PREENA = 1 to load the default words into R0 to R5. If changing the default words is required, program RX/TX control register with PREENA = 0 and then program any or all of R0 to R5. PREENA should also be set to 0 when sending SX R1, SX R2, and RX/TX control register words before each time slot in normal operation. The data is stored in R0 to R5 as long as VDDBB (pin 43) is supplied with power.
PDETVCC
Power detector bias [21]
PREENA
Load default words [22]
NU
Not used [23]
Not used
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Table 16. Register 0: Auxiliary Control
Symbol
ADDR GMC_BYP SK_BYP DC_BYP1
Function
Address bits [3:0]. Must be set to 0001b (see Table 12) Bypass GMC stage [4] Bypass S-K stage [5] Bypass first DC OC loop [6]
State Description
Default (Binary)
0 enables gmC filter stage 1 disables and bypasses gmC filter stage 0 enables Sallen-Key filter stage 1 disables and bypasses Sallen-Key filter stage 0 enables first DC offset correction loop 1 disables and bypasses first DC offset correction loop 0 enables second DC offset correction loop 1 disables and bypasses second DC offset correction 0 enables third DC offset correction loop 1 disables and bypasses third DC offset correction Not used 0 disables TXVCO 1 enables TXVCO via TXENA (Pin4) Reserved, must be programmed to default value Not Used Reserved, must be programmed to default value Reserved, must be programmed to default value 0 disables DFC 1 enables DFC 0 disables internal UHF VCO 1 enables internal UHF VCO Reserved, must be programmed to default value 0 disables IP2 calibration 1 enables IP2 calibration Not used Not used
0 0 0
DC_BYP2 DC_BYP3 NU TVCOEN RSVD NU RSVD RSVD DFCPLLENA UHFVCOENA RSVD CALENA NU NU
Bypass second DC OC loop [7] Bypass second DC OC loop [8] Not used [9] TXVCO Select [10] Reserved [12:11] Not Used [13] Reserved [14] Reserved [15] DFC Enable [16] UHFVCO Enable [17] Reserved[20:18] Enable IP2 Cal [21] Not used[22] Not used[23]
0 0 0 1 10 0 0 0 1 1 011 1 0 0
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Data Sheet I CX74063-34/-35/-36
Table 17. Register 2: DC Offset Timing
Symbol
ADDR DCOCL1 DCOCL2 DCOCL3 FEENA_TIM NU NU NU
Function
Address bits [3:0]. Must be set to 1001b (see Table 12) DCOC control [7:4] DCOC control [12:8] DCOC control [16:13] FEENA relative to initial track [20:17] Not used [21] Not used [22] Not used [23]
State Description
Default (Binary)
Tracking timing for DCOC1 (tT_H1 = (DCOCL1 x 64 x R)/Fref ) (Note 1) Tracking timing for DCOC2 (tT_H2 = (DCOCL2 x 64 x R)/Fref ) (Note 1) Tracking timing for DCOC3 (tT_H3 = (DCOCL3 x 128 x R)/Fref ) (Note 1) Front end enable timing (tFEENA = (FEENA_TIM x 128 x R)/Fref ) (Note 1) Not used Not used Not used
0100 (20 s with 13 MHz fREF) 01100 (60 s with 13 MHz fREF) 0110 (60 s with 13 MHz fREF) 0100 (40 s with 13 MHz fREF) 0 0 0
Note 1: See Figure 4 and Figure 5.
Table 18. Register 3: IP2 Calibration
Symbol
ADDR ADDR_SEL RSVD CORR_DATA
Function
Address bits [5:0]. Must be set to 001101b (see Table 12) Channel selection [6] Reserved [7] IP2 correction coefficient [15:8] 0 selects Q channel 1 selects I channel
State Description
Must be set to 1 for correct operation Coefficient for adjustment of receiver IP2 Bit [15] sets polarity: 0 = Positive 1 = Negative Bit [14:8] 1111111 minimum correction * * * 0000000 maximum correction Bit [14] = MSB Bit [8] = LSB
NU
Not used [23:16]
Not used
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Table 19. Register 4: PAC Timing Control
Symbol
ADDR RSVD PAC_TIME
Function
Address bits [5:0]. Must be set to 011101b (see Table 12) Reserved [11:6] PAC timing control [19:12]
State Description
Default (Binary)
Reserved. Must be set to default value. Bit [19:12] sets timing for PAC pedestal. When all bits = 0, no pedestal. Bit [12] = MSB = 1024/fPFD = 78.7 s for fPFD = 13 MHz Bit [19] = LSB = 8/fPFD = 0.615 s for fPFD = 13 MHz
000010 10011010 = 54.769 s
RSVD
Reserved [23:20]
Reserved. Must be set to default value.
0100
Table 20. Register 6: VCXO Control
Symbol
Function Description
Internal Power-On Value (Binary)
Recommended Operational Value (Binary)
ADDR CAP_A
Address bits [6:0]. Must be set to 0101101b (see Table 12) Bit [11:7] capacitor A array control. Binary weighted. Bit [11] = LSB = 1/8 pF Bit [7] = MSB = 2 pF Array composition = 2 pF, 1 pF, 0.5 pF, 0.25 pF, 0.125 pF Determined during a onetime factory calibration 00001
CAP_B
Bit [15:12] capacitor B array control. Binary weighted. Bit [15] = LSB = 1/32 pF Bit [12] = MSB = 1/4 pF Array composition = 0.25 pF, 0.125 pF, 0.065 pF, 0.03125 pF
0000
RSVD Note:
Bit [23:16] reserved Programmed values in this register are not maintained with VDDBB (pin 43).
00000000
00000000
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Data Sheet I CX74063-34/-35/-36
Table 21. Register 7: VCXO Control
Symbol
Function Description
Internal Power-On Value (Binary)
Recommended Operational Value (Binary)
ADDR I_VCXO
Address bits [6:0]. Must be set to 1101101b (see Table 12) Bit [10:7] negative resistance current control. Binary weighted. Negative logic (on = low, off = high) Bit [10] = LSB = 8 A Bit [7] = MSB = 64 A Stepped values = 64 A, 32 A, 16 A, 8 A 0101 1001
RSVD Note:
Bit [23:11] reserved. Must be set to default value.
0000000000000
0000000001110 (Must Use)
Programmed values in this register are not maintained with VDDBB (pin 43).
DATA tCS CLOCK tCWH
S23
S22
S1
S0 tCH
tES tCWL tEW
LE
C898
Figure 9. Serial Data Input Timing Diagram For Transceiver
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Data Sheet I CX74063-34/-35/-36
7
0 RX
1
2
3 TX
4
5 Mon
6
RXENA Internal DCOC 1 Internal DCOC 2 Internal DCOC 3 Internal FEENA SXENA LE TXENA
120 s 20 s 40 s 60 s 10 s 50 s 240 s 240 s 10 s (Note 1)
PAC_TIME
OFFSET GEN TIMING PAVAPC TX I/Q TRSW Enable FREF (not to scale) 25 s (Note 1) 0.7 V
PA RAMP Voltage
Note 1: This timing depends on circuitry other than the CX74063.
C1330
Figure 10. CX74063-3x Signal Timing Example (Normal Operation)
SXENA Preset=0 Band=GSM GSM IP2 I GSM IP2 Q Preset=0 DCS/PCS IP2 I Band=DCS/PCS DCS/PCS IP2 Q DCOC timing VCXO Control 1 VCXO Control 2
Preset=1 DATA
CLK
LE
Note 1
Note 1
VDDBB (pin 43)
Note 2
FREF (not to scale)
Note 1. LE should be low before the next clock goes high. Note 2. VDDBB, pin 43, is required to hold the register settings. If VDDBB is not maintained high, the power-on programming sequence needs to be added in front of each normal slot programming sequence.
C1329
Figure 11. CX74063-3x Register Programming Sequence and Timing Example (Initialization After Power Up)
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Data Sheet I CX74063-34/-35/-36
Receiver Data
Table 22. Recommended EGSM900/GSM850 AGC Data (1 of 2) (AGC Setpoint = -25.2 dBV = 55.0 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 0 4
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 96.8 94.8 92.8 90.8 88.8 86.8 84.8 82.8 80.8 78.8 76.8 74.8 72.8 70.8 68.8 66.8 64.8 62.8 60.8 58.8 56.8 54.8 52.8 50.8 48.8 46.8 44.8 42.8 40.8
I/Q Output (dBV) From
-26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2
To
-24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 -5 -5
40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 22 22 22 22 22 22 22 22 22 22 22
10 10 10 10 10 10 10 10 10 10 10 10 -2 -2 -2 -2 -2 -2 10 10 10 -2 -2 -2 -2 -2 -2 10 10
18 18 18 12 12 12 6 6 6 0 0 0 6 6 6 0 0 0 0 0 0 6 6 6 0 0 0 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
40
NOVEMBER 25, 2003
Skyworks Solutions, Inc., Proprietary and Confidential
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103116C
Data Sheet I CX74063-34/-35/-36
Table 22. Recommended EGSM900/GSM850 AGC Data (2 of 2) (AGC Setpoint = -25.2 dBV = 55.0 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-52 -50 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -50 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 0 0
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 38.8 36.8 34.8 32.8 30.8 28.8 26.8 24.8 22.8 20.8 18.8 16.8 14.8 12.8 10.8 8.8 6.8 6.8 6.8
I/Q Output (dBV) From
-26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -26.2 -24.2 -22.2
To
-24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -24.2 -22.2 -20.2
-5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
10 10 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2
0 0 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 12 12 12 6 6 6 0 0 0 0 0
Skyworks Solutions, Inc., Proprietary and Confidential
103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
41
NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
Table 23. Recommended DCS1800 AGC Data (1 of 2) (AGC Setpoint = -24.2 dBV = 61.7 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 2 0
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 97.8 95.8 93.8 91.8 89.8 87.8 85.8 83.8 81.8 79.8 77.8 75.8 73.8 71.8 69.8 67.8 65.8 63.8 61.8 59.8 57.8 55.8 53.8 51.8 49.8 47.8 45.8 43.8 41.8 39.8
I/Q Output (dBV) From
-25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2
To
-23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 -7 -7
40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 22 22 22 22 22 22 22 22 22 22 22
10 10 10 10 10 10 10 10 10 10 10 10 10 -2 -2 -2 -2 -2 -2 10 10 10 10 -2 -2 -2 -2 -2 10 10
24 18 18 18 12 12 12 6 6 6 0 0 0 6 6 6 0 0 0 0 0 0 6 6 6 0 0 0 6 6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
42
NOVEMBER 25, 2003
Skyworks Solutions, Inc., Proprietary and Confidential
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103116C
Data Sheet I CX74063-34/-35/-36
Table 23. Recommended DCS1800 AGC Data (2 of 2) (AGC Setpoint = -24.2 dBV = 61.7 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-50 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 -5.0 37.8 35.8 33.8 31.8 29.8 27.8 25.8 23.8 21.8 19.8 17.8 15.8 13.8 11.8 9.8 7.8 5.8 5.8
I/Q Output (dBV) From
-25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -25.2 -23.2
To
-23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -23.2 -21.2
-7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7 -7
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
10 10 10 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2
0 0 0 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 18 12 12 12 6 6 6 0 0 0
Skyworks Solutions, Inc., Proprietary and Confidential
103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
43
NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
Table 24. Recommended PCS1900 AGC Data (1 of 2) (AGC Setpoint = -25.4 dBV = 53.7 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-110 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -108 -106 -104 -102 -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 -78 -76 -74 -72 -70 -68 -66 -64 -62 -60 -58 -56 -54 -52 -50 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 0 4
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 96.6 94.6 92.6 90.6 88.6 86.6 84.6 82.6 80.6 78.6 76.6 74.6 72.6 70.6 68.6 66.6 64.6 62.6 60.6 58.6 56.6 54.6 52.6 50.6 48.6 46.6 44.6 42.6 40.6 38.6
I/Q Output (dBV) From
-26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4
To
-24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4
15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 -5 -5
40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 40 22 22 22 22 22 22 22 22 22 22 22
10 10 10 10 10 10 10 10 10 10 10 10 10 -2 -2 -2 -2 -2 -2 10 10 10 -2 -2 -2 -2 -2 -2 10 10
24 18 18 18 12 12 12 6 6 6 0 0 0 6 6 6 0 0 0 0 0 0 6 6 6 0 0 0 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18 18
44
NOVEMBER 25, 2003
Skyworks Solutions, Inc., Proprietary and Confidential
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103116C
Data Sheet I CX74063-34/-35/-36
Table 24. Recommended PCS1900 AGC Data (2 of 2) (AGC Setpoint = -25.4 dBV = 53.7 mVrms)
Antenna Input External (dBm) Front End Losses From To (dB)
-50 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -48 -46 -44 -42 -40 -38 -36 -34 -32 -30 -28 -26 -24 -22 -20 -18 -16 -14 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2 -4.2
LNA (dB)
Mixer (dB)
LPF (dB)
VGA1 (dB)
VGA1 Fine (dB)
2 0 4 2 0 4 2 0 4 2 0 4 2 0 4 2 0 0
Aux (dB)
VGA2 (dB)
Internal Total InterVoltage Stage Gain Losses (dB) (dB)
-6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 -6.2 36.6 34.6 32.6 30.6 28.6 26.6 24.6 22.6 20.6 18.6 16.6 14.6 12.6 10.6 8.6 6.6 4.6 4.6
I/Q Output (dBV) From
-26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -26.4 -24.4
To
-24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -24.4 -22.4
-5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5 -5
22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22
10 10 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2
0 0 6 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18 18 18 18 18 18 18 18 12 12 12 6 6 6 0 0 0 0
101514D 10_071101
Figure 12. Typical Baseband Frequency Response
Skyworks Solutions, Inc., Proprietary and Confidential
103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
45
NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
sec
101514D 11_071101
Figure 13. Typical Differential Delay Response Table 25. EGSM900/GSM850 LNA S11 (Normalized to 50 )
Frequency (MHz)
869.0 878.1 887.2 896.3 905.4 914.5 923.6 932.7 941.8 950.9 960.0
S11
0.386 - 0.632j 0.438 - 0.630j 0.454 - 0.629j 0.420 - 0.639j 0.403 - 0.642j 0.398 - 0.646j 0.371 - 0.653j 0.376 - 0.653j 0.379 - 0.657j 0.343 - 0.664j 0.350 - 0.664j
46
NOVEMBER 25, 2003
Skyworks Solutions, Inc., Proprietary and Confidential
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103116C
Data Sheet I CX74063-34/-35/-36
Table 26. DCS1800 LNA S11 (Normalized to 50 )
Frequency (MHz)
1805.0 1812.5 1820.0 1827.5 1835.0 1842.5 1850.0 1857.5 1865.0 1872.5 1880.0
S11
0.0205 - 0.649j 0.205 - 0.689j 0.275 - 0.704j 0.299 - 0.710j 0.319 - 0.713j 0.326 - 0.718j 0.316 - 0.722j 0.306 - 0.722j 0.307 - 0.722j 0.300 - 0.724j 0.287 - 0.724j
Table 27. PCS1900 LNA S11 (Normalized to 50 )
Frequency (MHz)
1930 1936 1942 1948 1954 1960 1966 1972 1978 1984 1990
S11
0.237 - 0.583j 0.362 - 0.595j 0.432 - 0.591j 0.472 - 0.589j 0.489 - 0.591j 0.488 - 0.597j 0.483 - 0.600j 0.485 - 0.600j 0.484 - 0.600j 0.475 - 0.603j 0.465 - 0.605j
Skyworks Solutions, Inc., Proprietary and Confidential
103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
47
NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
Table 28. Typical EGSM and GSM850 Band Noise Figure vs. Gain Data
Gain
100.8 98.8 96.8 94.8 92.8 90.8 88.8 86.8
NF
3.17 3.17 3.17 3.18 3.20 3.22 3.26 3.31
Gain
84.8 82.8 80.8 78.8 76.8 74.8 72.8 70.8
NF
3.38 3.48 3.59 3.73 4.90 5.44 6.08 6.82
Gain
68.8 66.8 64.8 62.8 60.8 58.8 56.8 54.8
NF
7.60 8.39 11.80 12.77 13.71 18.43 19.79 21.16
Gain
52.8 50.8 48.8 46.8 44.8 42.8 40.8 38.8
NF
22.50 23.76 24.92 30.21 31.29 32.37 33.39 38.32
Gain
36.8 34.8 32.8 30.8 28.8 26.8 24.8 22.8
NF
39.71 41.11 42.46 43.73 44.89 42.70 44.02 45.24
Gain
20.8 18.8 16.8 14.8 12.8 10.8
NF
43.56 45.01 46.39 45.89 47.58 49.25
60.00
50.00
Noise Figure (dB)
40.00
30.00
20.00
10.00
0.00 0 20 40 60 RX Voltage Gain (dB) 80 100 120
101514F 15_111201
Figure 14. Typical EGSM and GSM850 Band Noise Figure vs. Voltage Gain Curve (CX74063-3x Only, No Front End Loss)
48
NOVEMBER 25, 2003
Skyworks Solutions, Inc., Proprietary and Confidential
[781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103116C
Data Sheet I CX74063-34/-35/-36
Table 29. Typical EGSM and GSM850 Band Dynamic Range Data (Includes 4.0 dB Front End Loss)
Input
-109.0 -107.0 -105.0 -103.0 -101.0 -99.0 -97.0 -95.0 -93.0 -91.0 -89.0 -87.0 -85.0 -83.0 -81.0 -79.0
Noise Floor
-113.0 -113.0 -113.0 -113.0 -113.0 -113.0 -112.9 -112.9 -112.8 -112.7 -112.5 -112.3 -112.1 -110.8 -110.0 -109.2
P1dB
-78.6 -76.6 -74.6 -72.6 -70.6 -68.7 -66.9 -65.2 -63.7 -62.4 -61.4 -60.5 -59.9 -54.8 -53.8 -53.0
Gain
97.8 95.8 93.8 91.8 89.8 87.8 85.8 83.8 81.8 79.8 77.8 75.8 73.8 71.8 69.8 67.8
Input
-77.0 -75.0 -73.0 -71.0 -69.0 -67.0 -65.0 -63.0 -61.0 -59.0 -57.0 -55.0 -53.0 -51.0 -49.0 -47.0
Noise Floor
-108.2 -107.1 -106.0 -102.9 -101.6 -100.4 -96.4 -94.9 -93.4 -91.8 -90.3 -88.9 -83.8 -82.6 -81.3 -79.9
P1dB
-52.4 -52.0 -51.8 -43.4 -42.5 -41.9 -36.9 -35.9 -35.2 -34.6 -34.3 -34.0 -24.3 -23.2 -22.3 -21.7
Gain
65.8 63.8 61.8 59.8 57.8 55.8 53.8 51.8 49.8 47.8 45.8 43.8 41.8 39.8 37.8 35.8
Input
-45.0 -43.0 -41.0 -39.0 -37.0 -35.0 -33.0 -31.0 -29.0 -27.0 -25.0 -23.0 -21.0 -19.0 -17.0 -15.0
Noise Floor
-78.6 -74.5 -72.9 -71.4 -69.8 -68.3 -66.9 -66.9 -65.2 -63.4 -62.3 -60.3 -58.4 -56.7 -54.7 -52.7
P1dB
-21.2 -18.1 -17.7 -17.4 -17.2 -17.0 -17.0 -16.9 -16.9 -16.9 -16.8 -16.8 -16.8 -16.8 -16.8 -16.8
Gain
33.8 31.8 29.8 27.8 25.8 23.8 21.8 19.8 17.8 15.8 13.8 11.8 9.8 7.8 5.8 3.8
-10.00
-20.00 P1dB -40.00
dBm
-60.00 Input -80.00 Noise Floor -100.00
-120.00 -120.0
-100.0
-80.0
+ 4.0 dB Front End Loss
-60.0 Antenna Input (dBm)
-40.0
-20.0
0.0
101514F 16_111901
Figure 15. Typical EGSM and GSM850 Band Dynamic Range vs. Antenna Input Curve
Skyworks Solutions, Inc., Proprietary and Confidential
103116C [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWORKSINC.COM I WWW.SKYWORKSINC.COM
49
NOVEMBER 25, 2003
Data Sheet I CX74063-34/-35/-36
Table 30. Typical DCS1800 Band Noise Figure vs. Gain Data
Gain
100 98 96 94 92 90 88 86
NF
3.7 3.7 3.7 3.7 3.7 3.7 3.8 3.8
Gain
84 82 80 78 76 74 72 70
NF
3.9 4.0 4.1 4.3 5.5 6.1 6.7 7.5
Gain
68 66 64 62 60 58 56 54
NF
8.3 9.1 12.6 13.6 14.5 19.2 20.6 22.0
Gain
52 50 48 46 44 42 40 38
NF
23.3 24.6 25.7 32.0 33.0 34.1 35.2 36.2
Gain
36 34 32 30 28 26 24 22
NF
41.1 42.5 43.9 45.3 46.5 47.7 45.5 46.8
Gain
20 18 16 14 12 10
NF
48.0 46.4 47.8 49.2 48.7 50.4
60.00
50.00
Noise Figure (dB)
40.00
30.00
20.00
10.00
0.00 0 20 40 60 RX Voltage Gain (dB) 80 100 120
101514F 17_111201
Figure 16. Typical DCS1800 Band Noise Figure vs. Voltage Gain Curve (CX74063-3x Only; No Front End Loss)
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Data Sheet I CX74063-34/-35/-36
Table 31. Typical DCS1800 Band Dynamic Range Data (Includes 4.2 dB Front End Loss)
Input
-109.0 -107.0 -105.0 -103.0 -101.0 -99.0 -97.0 -95.0 -93.0 -91.0 -89.0 -87.0 -85.0 -83.0 -81.0 -79.0
Noise Floor
-113.0 -113.0 -113.0 -113.0 -113.0 -113.0 -112.9 -112.9 -112.8 -112.7 -112.5 -112.3 -112.1 -110.8 -110.0 -109.2
P1dB
-78.6 -76.6 -74.6 -72.6 -70.6 -68.7 -66.9 -65.2 -63.7 -62.4 -61.4 -60.5 -59.9 -54.8 -53.8 -53.0
Gain
97.8 95.8 93.8 91.8 89.8 87.8 85.8 83.8 81.8 79.8 77.8 75.8 73.8 71.8 69.8 67.8
Input
-77.0 -75.0 -73.0 -71.0 -69.0 -67.0 -65.0 -63.0 -61.0 -59.0 -57.0 -55.0 -53.0 -51.0 -49.0 -47.0
Noise Floor
-108.2 -107.1 -106.0 -102.9 -101.6 -100.4 -96.4 -94.9 -93.4 -91.8 -90.3 -88.9 -83.8 -82.6 -81.3 -79.9
P1dB
-52.4 -52.0 -51.8 -43.4 -42.5 -41.9 -36.9 -35.9 -35.2 -34.6 -34.3 -34.0 -24.3 -23.2 -22.3 -21.7
Gain
65.8 63.8 61.8 59.8 57.8 55.8 53.8 51.8 49.8 47.8 45.8 43.8 41.8 39.8 37.8 35.8
Input
-45.0 -43.0 -41.0 -39.0 -37.0 -35.0 -33.0 -31.0 -29.0 -27.0 -25.0 -23.0 -21.0 -19.0 -17.0 -15.0
Noise Floor
-78.6 -74.5 -72.9 -71.4 -69.8 -68.3 -66.9 -66.9 -65.2 -63.4 -62.3 -60.3 -58.4 -56.7 -54.7 -52.7
P1dB
-21.2 -18.1 -17.7 -17.4 -17.2 -17.0 -17.0 -16.9 -16.9 -16.9 -16.8 -16.8 -16.8 -16.8 -16.8 -16.8
Gain
33.8 31.8 29.8 27.8 25.8 23.8 21.8 19.8 17.8 15.8 13.8 11.8 9.8 7.8 5.8 3.8
-10.00
-20.00 P1dB -40.00
dBm
-60.00 Input -80.00 Noise Floor -100.00
-120.00 -120.0
-100.0
-80.0
+ 4.2 dB Front End Loss
-60.0 Antenna Input (dBm)
-40.0
-20.0
0.0
101514F 18_111201
Figure 17. Typical DCS1800 Band Dynamic Range vs. Antenna Input Curve
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Data Sheet I CX74063-34/-35/-36
Table 32. Typical PCS1900 Band Noise Figure vs. Gain Data
Gain
98.8 96.8 94.8 92.8 90.8 88.8 86.8 84.8
NF
4.2 4.2 4.2 4.2 4.2 4.3 4.3 4.4
Gain
82.8 80.8 78.8 76.8 74.8 72.8 70.8 68.8
NF
4.5 4.6 4.7 4.9 6.3 6.9 7.6 8.4
Gain
66.8 64.8 62.8 60.8 58.8 56.8 54.8 52.8
NF
9.3 10.1 13.7 14.7 15.6 20.4 21.8 23.1
Gain
50.8 48.8 46.8 44.8 42.8 40.8 38.8 36.8
NF
24.5 25.8 26.9 33.2 34.2 35.3 36.4 37.4
Gain
34.8 32.8 30.8 28.8 26.8 24.8 22.8 20.8
NF
42.3 43.7 45.1 46.5 47.7 48.9 46.7 48.0
Gain
18.8 16.8 14.8 12.8 10.8 8.8 6.8
NF
49.2 47.6 49.0 50.4 49.9 51.6 53.3
60.00
50.00
Noise Figure (dB)
40.00
30.00
20.00
10.00
0.00 0 20 40 60 RX Voltage Gain (dB) 80 100 120
101514F 19_111901
Figure 18. Typical PCS1900 Band Noise Figure vs. Voltage Gain Curve (CX74063-3x Only; No Front End Loss)
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Data Sheet I CX74063-34/-35/-36
Table 33. Typical PCS1900 Band Dynamic Range Data (Includes 4.2 dB Front End Loss)
Input
-109.0 -107.0 -105.0 -103.0 -101.0 -99.0 -97.0 -95.0 -93.0 -91.0
-
Noise Floor
-112.5 -112.5 -112.5 -112.5 -112.5 -112.5 -112.4 -112.4 -112.3 -112.1 -112.0 -111.8 -111.5 -110.0 -109.3 -108.4
P1dB
-77.4 -75.4 -73.4 -71.4 -69.4 -67.5 -65.7 -64.0 -62.5 -61.2 -60.2 -59.3 -58.7 -53.6 -52.6 -51.8
Gain
96.6 94.6 92.6 90.6 88.6 86.6 84.6 82.6 80.6 78.6 76.6 74.6 72.6 70.6 68.6 66.6
Input
-77.0 -75.0 -73.0 -71.0 -69.0 -67.0 -65.0 -63.0 -61.0 -59.0 -57.0 -55.0 -53.0 -51.0 -49.0 -47.0
Noise Floor
-107.4 -106.3 -105.2 -102.0 -100.7 -99.5 -95.4 -93.9 -92.4 -90.9 -89.4 -88.0 -82.8 -81.6
-
P1dB
-51.2 -50.8 -50.6 -42.2 -41.3 -40.7 -35.7 -34.7 -34.0 -33.4 -33.1 -32.8 -23.3 -22.2 -21.4 -20.8
Gain
64.6 62.6 60.6 58.6 56.6 54.6 52.6 50.6 48.6 46.6 44.6 42.6 40.6 38.6 36.6 34.6
Input
-45.0 -43.0 -41.0 -39.0 -37.0 -35.0 -33.0 -31.0 -29.0 -27.0 -25.0 -23.0 -21.0 -19.0 -17.0 -15.0
Noise Floor
-77.7 -73.5 -72.0 -70.4 -68.9 -67.4 -66.0 -66.3 -64.6 -62.9 -61.8 -59.9 -58.0 -56.3 -54.3 -52.4
P1dB
-20.3 -17.6 -17.2 -17.0 -16.8 -16.7 -16.6 -16.6 -16.5 -16.5 -16.5 -16.5 -16.5 -16.5 -16.5 -16.5
Gain
32.6 30.6 28.6 26.6 24.6 22.6 20.6 18.6 16.6 14.6 12.6 10.6 8.6 6.6 4.6 2.6
89.0
-87.0 -85.0 -83.0 -81.0 -79.0
80.3
-79.0
-10.00
-20.00 P1dB -40.00
dBm
-60.00 Input -80.00 Noise Floor -100.00
-120.00 -120.0
-100.0
-80.0
+4.2 dB Front End Loss
-60.0 Antenna Input (dBm)
-40.0
-20.0
0.0
101514F 20_111901
Figure 19. Typical PCS1900 Band Dynamic Range vs. Antenna Input Curve
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Data Sheet I CX74063-34/-35/-36
50 45 Control Sensitivity (MHz/V) 40 35 30 25 20 15 10 5 Typical Performance Specification Limits
0 1100
1200
1300 1400 VCO Frequency (MHz)
1500
1600
101514F 21_111901
Figure 20. Typical Control Sensitivity, UHF VCO
35 30 Control Sensitivity (MHz/V) 25 20 15 10 5 0 750 Typical Performance Specification Limits
800
850 VCO Frequency (MHz)
900
950
101514F 22_111901
Figure 21. Typical Control Sensitivity, Low Band TX VCO
30 25 20 Specification Limits 15 10 5 0 1600 Typical Performance
Control Sensitivity (MHz/V)
1650
1700
1750 1850 1800 VCO Frequency (MHz)
1900
1950
2000
101514F 23_111901
Figure 22. Typical Control Sensitivity, High Band TX VCO
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Data Sheet I CX74063-34/-35/-36
Transmitter Data
RBW VBW SWT 30 kHz 30 kHz 5 ms 20 dB RF Att Mixer -20 dBm dBm Unit
5 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -95 Center 836.4 MHz
1 1 [T1] = 2.61 dBm 836.40000000 MHz 1 [T1] = -67.91 dB -400.00000000 kHz 2 [T1] = -67.69 dB 400.00000000 kHz
Relative Power (dB)
1
2
100 kHz/
Span 1 MHz
S094
Figure 23. Typical GSM850 Band Output Spectrum
RBW VBW SWT
30 kHz 30 kHz 5 ms
20 dB RF Att Mixer -20 dBm dBm Unit
5 0 -10 -20 -30 -40 -50 -60
1
1 1 [T1] = 3.02 dBm 902.40000000 MHz 1 [T1] = -68.37 dB -400.00000000 kHz 2 [T1] = -87.71 dB 400.00000000 kHz
Relative Power (dB)
2
-70 -80 -90 -95 Center 902.4 MHz 100 kHz/ Span 1 MHz
S095
Figure 24. Typical EGSM Band Output Spectrum
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Data Sheet I CX74063-34/-35/-36
RBW VBW SWT
30 kHz 30 kHz 5 ms
20 dB RF Att Mixer -20 dBm dBm Unit
5 0 -10 -20 -30 -40 -50 -60
1
1 1
[T1] = 0.09 dBm 1.74780000 GHz
1 [T1] = -67.66 dB -400.00000000 kHz 2
[T1] = -67.32 dB 400.00000000 kHz
Relative Power (dB)
2
-70 -80 -90 -95 Center 1.7478 GHz 100 kHz/ Span 1 MHz
S096
Figure 25. Typical DCS Band Output Spectrum
RBW VBW SWT
30 kHz 30 kHz 5 ms
20 dB RF Att Mixer -20 dBm dBm Unit
5 0 -10 -20 -30 -40 -50 -60
1
1 1
[T1] = 0.75 dBm 1.88000000 GHz
1 [T1] = -64.79 dB -400.00000000 kHz 2
[T1] = -64.58 dB 400.00000000 kHz
Relative Power (dB)
2
-70 -80 -90 -95 Center 1.88 GHz 100 kHz/ Span 1 MHz
S097
Figure 26. Typical PCS Band Output Spectrum
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TXVCO TUNE TX1800/TX1900 TX900 VCCTXVCO VCC4 RXIP RXIN RXQP RXQN VCC3 VCCUHF UHFTUNE UHFBYP
PAVAPC
TXIP
Figure 27. Typical CX74063-3x Application Circuit
1 C21 1.2 pF 5 L2 6.8 nH
346
16 17 18 19 20 21 22 23 24 25 26 27 28 R7 39 k C16 470 pF C15 470 pF
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V_RF
L5 1.5 nH 1 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56 55 54 53 52 51 50 49 48 47 46 45 44
F3 DCS SAW
2
DCS RX input
IN GROUND
1 C23 0.5 pF L3 3.3 nH 346
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C28 1.8 pF C2 220 pF R2 2 k
OUT
BBVAPC
TXIN TXQP TXQN TXIFP TXIFN VCC2 CAPIP CAPIN CAPQP CAPQN
103116C
V_RF
RF in
C1 100 nF
PA
VSYN
RF out
Coupler To Antenna
PAVAPC
V_RF
C4 1 F C27 0.1 F C26 1 nF C25 1 nF
R3 270  C8 39 pF L6 220 nH L4 10 nH
RXQN RXQP RXIN RXIP +
C17 39 pF
RF Detector
V_RF
C3 1 nF R1 5.6 k
R6 680 
C18 3.9 nF
C7 8.2 nF
C5 680 pF
VLogic VSYN
C12 1 nF 3 4 5 6 7 8 9 R5 390  R4 510  11 12 13 14 15 R8 50  10
RXENA TXENA
2
VCXO_EN
VDDBB LE CLK DATA XTAL TUNE SXENA VCCFN_CP UHFCPO
LE CLK DATA XTAL TUNE SXENA
C11 1 nF
Crystal
1000 pF
DCS/PCS TX to PA
CX74063-34/-35/-36 Multi-Band GSM Transceiver
V_RF
V_RF
GSM TX to PA
F1 GSM SAW
2
RXENA TXENA PCO VCXO_EN PDETVCC VCC1 TXCPO TXINP LNA900IN GNDLNA900 LNA1800IN PDET LNA1900IN NC NC
GNDFN XTAL VCCF VCCD GNDD XTAL BUF LPFADJ
C13 0.1F C14 0.1F
IN GROUND
L1 10 nH
OUT
5
GSM RX input
To Baseband
C22 100 nF
V_RF
PCS RX input
2
F2 PCS SAW IN GROUND
1 346 C24 1.0 pF
OUT
5
TxQN TxQP TxIN TxIP
22 pF
PAVAPC BBVAPC
82 nH
C1331
Data Sheet I CX74063-34/-35/-36
NOVEMBER 25, 2003
57
Data Sheet I CX74063-34/-35/-36
8.00  0.10 Pin 1
0.38  0.08 Pin 1
R2.70 Ref 0.50 Ref
8.00  0.10
0.30  0.05
Top View
Bottom View
1.00  0.10
Side View
All dimensions are in millimeters
C1339
Figure 28. 56-Pin RFLGA Package Dimension Drawing (CX74063-34 and CX74063-35 Options)
8.00  0.10 Pin 1 0.38  0.08
0.56 Ref
Pin 1
R2.70 Ref
0.50 Ref
8.00  0.10
R0.25 (12x)
0.30  0.05
Top View
Bottom View
1.00  0.10
Side View
All dimensions are in millimeters
S288
Figure 29. 56-Pin RFLGA Package Dimension Drawing (CX74063-36 Option)
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Data Sheet I CX74063-34/-35/-36
12.00  0.10 4.00  0.10
2.00  0.10 Pin #1 indicator
B
1.50  0.10
1.75  0.10
7.50  0.10
1.50  0.25
o 7 Max
A
A
B
0.318  .02
o 8 Max
1.73  0.10 8.40  0.10 8.40  0.10
Notes: 1. Carrier tape material: black conductive polycarbonate or polystyrene 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 13.3 mm width 4. All measurements are in millimeters
S109a
A
B
Figure 30. 56-Pin RFLGA Tape and Reel Dimensions (CX74063-34/36 Options)
2.00  0.10
12.00  0.10 4.00  0.10
B
Pin #1 indicator
1.50  0.10
1.75  0.10
7.50  0.10
1.50  0.25
o 7 Max
A
A
B
0.318  .02
o 8 Max
1.73  0.10 8.40  0.10 8.40  0.10
Notes: 1. Carrier tape material: black conductive polycarbonate or polystyrene 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 13.3 mm width 4. All measurements are in millimeters
S109
A
B
Figure 31. 56-Pin RFLGA Tape and Reel Dimensions (CX74063-35 Option)
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16.00 + 0.30/-0.10
16.00 + 0.30/-0.10
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Data Sheet I CX74063-34/-35/-36
Mark Pin 1 ID (Note 1)
CX74063-DD K16102.5 0325 USA
Brand line 1: Part Number (Note 2) Brand line 2: Lot Number and Lot Split Identifier (Note 2) Brand line 3: Date Code, Country of Origin (Note 2)
Note 1: Note 2:
The Pin 1 ID is a triangle or circle. Brand line 1. The Part Number format is CXPPPPP-DD. The CX prefix is the company identifier. P = five-digit part number, D = dash number (for example, -34, -35). The CX prefix may not appear on small devices. The Part Number may be followed by a "P" to indicate a prototype device. (Note 3) Brand line 2. Lot Number and Lot Split Identifier. The Lot Number format = 6 alphanumeric characters followed by a 1- or 2-digit Lot Split Identifier separated by a decimal point. The format is A12345.2 or A12345.21. (Note 3) Brand line 3. Date Code and Country of Origin. The Date Code should be the same for the entire Lot Number and Lot Split Identifier. The first two digits of the Date Code are the current accounting calendar year. The last two digits are the current accounting calendar week. The format is YYWW (for example, 0225). The Country of Origin is the full name of the country where assembly is completed (for example, Mexico). The Country of Origin may be abbreviated (for example, USA or CN) if backside marking is not possible because of size restrictions. (Note 3) A vendor-specified logo may appear below Brand line 3 (for example, ARM).
Note 3:
As long as the device form, fit, and function remain the same, the data in Brand lines 1-3 may change. For example, the Lot Number and Lot Split Identifier may change; the Date Code and Country of Origin may change if Skyworks selects a second assembly source.
C1403c
Figure 32. Typical Case Markings
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Data Sheet I CX74063-34/-35/-36
Ordering Information
Model Name
CX74063: MSL3/240, circular ground pad MSL3/260, circular ground pad MSL3/260, four-quadrant ground pad
Manufacturing Part Number
CX74063-34 CX74063-35 CX74063-36
Product Revision
(c) 2003 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks' Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKSTM PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THESE MATERIALS. SkyworksTM products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks' customers using or selling SkyworksTM products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. The following are trademarks of Skyworks Solutions, Inc.: SkyworksTM, the Skyworks symbol, "Single Package Radio"TM, SPRTM, and "Breakthrough Simplicity"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. GSMTM, "Global System for Mobile CommunicationsTM," and the GSM logo are trademarks of the GSM Association. RFLGATM is a trademark of Conexant Systems, Inc. Additional information, posted at www.skyworksinc.com, is incorporated by reference.
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General Information Skyworks Solutions, Inc. 20 Sylvan Rd. Woburn, MA 01801 www.skyworksinc.com