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CX74017

CX74017 DataSheet Conexant RF Transceiver for GSM/GPRS Applications

Transceiver GSM/GPRS Applications

Conexant

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CX74017 CX74017

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CX74017
RF Transceiver for Single, Dual, or Tri-Band GSM/GPRS Applications
Conexant's CX74017 transceiver is a highly integrated device for use in multi-band, Global System for Mobile communications (GSM) applications or General Packet Radio Service (GPRS) applications. The device requires a minimal number of external components to complete a GSM radio subsystem. The device's receiver uses a direct down-conversion architecture that eliminates the need for Intermediate Frequency (IF) components. The receiver consists of integrated Low Noise Amplifiers (LNAs), a quadrature demodulator, tunable receiver baseband filters, and a DC offset correction sequencer. In the transmit path, the device consists of an In-phase and Quadrature (I/Q) modulator within a frequency translation loop designed to perform frequency upconversion with high output spectral purity. This loop also contains a phasefrequency detector, a charge pump, a mixer, and buffers for the required isolation between RF output, Local Oscillator (LO), and IF ports. The transmitter also includes the entire transmit Voltage Controlled Oscillator (VCO) structure with no external tank required. The CX74017 also features an integrated, fully programmable, fractional-N synthesizer suitable for GPRS multi-slot operation. With the exception of the loop filter, the frequency synthesizer function is completely on-chip. The CX74017 device package and pin configuration are shown in Figure 1. A functional block diagram is shown in Figure 2. The signal pin assignments and functional pin descriptions are provided in Table 1.
TX900 NC NC NC VCCTXVCO VCC4 RXIP RXIN RXQP RXQN LON LOP VCC3
Features
* Direct down-conversion receiver eliminates the external image reject/IF filters * Integrated triple band LNAs with three separate inputs * 18 dB of RF gain range and 100 dB of baseband gain range * Gain selectable in 2 dB steps * Integrated receive baseband filters with tunable bandwidth * Integrated DC offset correction sequencer * Reduced filtering requirements with translation loop transmit architecture * Integrated transmit VCOs * Wide RF range for dual/ triple band operation * Single integrated, fully programmable fractional-N synthesizer suitable for multi-slot GPRS operation * Fully integrated UHF VCO * Separate enable lines for power management transmit, receive, and synthesizer modes * Supply voltage down to 2.7 V * Low external component count * Optional bypass of baseband filtering for use with high dynamic range Analog/Digital Converters (ADCs) for current savings * Interfaces to low dynamic range ADC * No digital post-processing required * 64-pin Land Grid Array (LGA) 9x9mm package
VCCUHF UHFTUNE
Applications
UHFBYP VDDBB LE CLK DATA LD_MUX SXENA VCCFN_CP UHFCPO GNDCP GNDFN FREF VCCF VCCD GNDD NC NC
TX1800/TX1900 TXVCOTUNE RXENA TXENA PCO1 PCO2 TXCPVCC VCC1 TXCPO TXINP LNA900IN GNDLNA900 LNA1800IN FEENA LNA1900IN NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
18 19 24 25 27 28 29 20 21 22 23 26 30 31 32
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
* GSM single, dual, or tri-band handsets with multislot capability * GPRS handsets and modules
64
63
62
61
60
59
58
57
56
55
54
53
52
51
FILTP TXIP TXIN TXQP TXQN TXIFP TXIFN VCC2 CAPIP CAPIN CAPQP CAPQN LPFADJ T_H
FILTN
50
C897
Figure 1. CX74017 Pinout - 64-Pin LGA (Top View) Data Sheet
Conexant Proprietary
Preliminary Data Subject to Change
100950B January 2, 2001
GSM RF Transceiver
CX74017
TxIN TxQN TxIP TxQP
TxIFP TxIFN
Tx path
TXINP
Tx RF in
+
FILTN FILTP
R
CP
TXCPO CNTL
TX900 TX1800 TX1900
N Sx
LO generation
UHFTune
Frac N
UHFCPO
SXENA RXENA TXENA FEENA T/H FREF LE DATA CLK BANDSEL1 BANDSEL2
GSM LNA
I MIX Out
VGA1
VGA2
LNA900 In
CAPIP CAPIN DCOC DCOC DCOC
RxIP RxIN
DCS LNA
Q MIX Out
VGA1
VGA2
LNA1800 In LNA1900 In
CAPQP CAPQN DCOC DCOC DCOC
RxQP RxQN
PCS LNA
Rx path
C900
Figure 2. CX74017 Transceiver Block Diagram
Technical Description
The CX74017 transceiver contains a receive path, a transmit path, and a synthesizer section as shown in Figure 2. The receive path consists of a triple band integrated LNA, quadrature demodulator section that performs direct down conversion, and baseband amplifier circuitry with I/Q outputs and three stages of DC offset correction. The transmit path consists of a vector modulator within a translation loop for frequency up-conversion. The fully integrated on-chip oscillator locked in an integrated fractional-N synthesizer loop comprises the synthesizer section. Each section of the CX74017 is separately enabled via the enable signals TXENA, RXENA, and SXENA. To control different modes of operation, a serial 24-bit word (bits S0 to S23) is written to the on-chip register. This 24-bit word is programmed using the 3-wire input signals CLK, DATA, and LE. To ensure that the data stays latched, the CX74017 must continue to be supplied with voltage although none of the
sections needs to be enabled. A separate power supply pin is provided for the digital sections that allow power supply operation compatible with modern digital baseband devices. Receive Path _______________________________________ The receive path of the CX74017 consists of an RF section and a baseband section. The RF section includes a programmable gain LNA and quadrature demodulator for each band. The baseband I/Q paths are made up of cascaded amplifier and low pass filter sections. An off-chip capacitor and three fixed poles of on-chip filtering provide rejection of strong in- and out-of-band blockers. A tunable, four-pole filter provides rejection of the adjacent channel blockers. Incorporated within the fixed pole filters are two switchable gain stages of 18 dB and 12 dB gain steps, respectively. Incorporated into the four- pole tunable filter is another programmable gain amplifier with a gain range from -2 to +32 dB, selectable in 2 dB steps. The output of the final filter feeds a rail-to-rail amplifier with a gain range from 0 to 30 dB, selectable in 6 dB steps.
100950B
2 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
CX74017
GSM RF Transceiver
Table 1. CX74017 Signal Descriptions Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Name
TX1800/TX1900 TXVCOTUNE RXENA TXENA PCO1 PCO2 TXCPVCC VCC1 TXCPO TXINP LNA900IN GNDLNA900 LNA1800IN FEENA LNA1900IN NC NC FILTN FILTP TXIP TXIN TXQP TXQN TXIFP TXINN VCC2 CAPIP CAPIN CAPQP CAPQN LPFADJ T_H
Description
DCS and PCS transmit VCO output (NC) Transmit VCO control input Receiver enable input Transmitter enable input Bi-directional control Bi-directional control Transmit charge pump supply LNA/transmit charge pump supply (LNA supply) Translation loop charge pump output Translation loop feedback input EGSM LNA input EGSM LNA emitter ground DCS LNA input Bi-directional front end enable input/output PCS LNA input No connect No connect TX IF output negative TX IF output positive TX I baseband input positive TX I baseband input negative TX Q baseband input positive TX Q baseband input negative TX IF filter output positive TX IF filter output negative Mixer/baseband supply Capacitor filter I positive Capacitor filter I negative Capacitor filter Q positive Capacitor filter Q negative LPF corner resistor Track and hold initiate
Pin #
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC
Name
No connect No connect
Description
GNDD VCCD VCCF FREF GNDFN GNDCP UHFCPO VCCFN_CP SXENA LD_MUX DATA CLK LE VDDBB UHFBYP UHFTUNE VCCUHF VCC3 LOP LON RXQN RXQP RXIN RXIP VCC4 VCCTXVCO NC NC NC TX900
Synthesizer digital ground Synthesizer digital supply Synthesizer analog supply Crystal reference input Synthesizer analog ground Synthesizer charge pump ground Synthesizer charge pump output Synthesizer charge pump supply Synthesizer enable input Synthesizer test output Data Clock Latch enable Digital CMOS supply Bypass capacitor for UHF VCO (NC) UHF VCO control input (NC) UHF VCO supply LO chain supply External LO input/internal LO monitor positive External LO input/internal LO monitor negative Receiver output Q negative Receiver output Q positive Receiver output I negative Receiver output I positive Baseband supply Transmit VCO supply (NC) No connect No connect No connect EGSM transmit VCO
The receiver architecture intrinsically defeats DC offsets generated through LO and blocker self-mixing. Random input referred offsets generated in the CX74017 must be calibrated out. Three calibration loops are required to ensure that DC offsets do not overload the baseband chain at any point. After compensation, the correction voltages are held in capacitors for the duration of the receive slot(s). Internal, onchip timing is provided to generate the track and hold signals for these calibration loops. The timing for these signals is relative to the T_H signal. The timing diagram for the calibration sequence for one DC offset correction in reference to the receive slot is shown in
100950B
Figure 3. First the CX74017 receiver is turned on (RXENA is set high). After time T1, the track and hold signal, T_H, places the DC compensation circuitry in the track mode for time T2. Then, there is a settling time, T3, before the front end is turned on (FEENA is set high). The front end must be turned on for time T4 before the receive slot begins. For more flexibility with baseband interfaces, the four-pole filter, its associated Variable Gain Amplifier (VGA), and DC offset correction can be bypassed and turned off for current savings. To minimize the post-PA filtering requirements, and any additional post-PA losses, the transmit path consists of a vector modulator within a frequency translation loop. The translation
3 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
GSM RF Transceiver
CX74017
loop consists of a Phase Frequency Detector (PFD) and charge pump, a mixer (with an operating range of 800 MHz to 2 GHz), an in-loop modulator, and two transmit VCOs. As shown in Figure 2, the loop functions as a Phase-Locked Loop (PLL) with a mixer and modulator in the feedback path. The on-chip LowPass Filter (LPF) following the mixer attenuates the unwanted sideband as well as harmonics. The two on-chip transmit VCOs are designed to meet EGSM, DCS, and PCS requirements. Synthesizer Section _________________________________ The CX74017 includes a fully integrated UHF VCO with an onchip LC tank. A single fractional-N synthesizer can phase lock the local oscillator used in both the transmit and the receive path to a precision frequency reference source. Fractional-N operation offers low phase noise and fast settling times, allowing for multiple slot applications such as GPRS. The frequency stepping function of the CX74017, with a 1 Hz accuracy, allows triple band operation in both transmit and receive bands without the requirement of a large VCO tuning range using only a single integrated on-chip UHF VCO. Control Interface ___________________________________ The transceiver and synthesizer are controlled by a three-wire interface. The receiver gain control, as well as the division ratios and charge pump currents in the synthesizer and transmitter,
can be programmed using 24-bit words. The transmitter, receiver, and synthesizer can be enabled separately. Electrical and Mechanical Specifications ________________ The absolute maximum ratings of the CX74017 are provided in Table 2. The recommended operating conditions are specified in Table 3. Table 4 provides the power consumption of the CX74017 in various operational modes. Electrical specifications are provided in Tables 5, 6, 7 and 8. Table 9 contains the band selection truth table. Table 10 and Table 11 show the function settings of the control bits in the serial interface. Figure 4 depicts a summarized description of each programming word for quick reference. The three-wire serial interface timing diagram is shown in Figure 5. Figure 6 shows the 64-pin CX74017 LGA package dimensions.
Electrostatic Discharge
The CX74017 contains Class 1 devices. The following Electrostatic Discharge (ESD) precautions are recommended: * * * * * Protective outer garments Handle device in ESD safeguarded work area Transport device in ESD shielded containers Monitor and test all ESD protection equipment Treat the CX74017 as extremely sensitive to ESD
TDMA Slots
Rx Slot
RxENA T1 T_H T2 T3 FEENA T4
C899
Figure 3. CX74017 Sample and Hold Timing Diagram
4 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017 Table 2. CX74017 Absolute Maximum Ratings Parameter
Supply voltage (VCC) Ambient operating temperature range Storage temperature range Input voltage range Maximum power dissipation -40 -50 GND
GSM RF Transceiver
Minimum
Maximum
3.6 +85 +125 VCC 600
Units
V C C V mW
NOTE: stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to maximum rating conditions for extended periods may reduce device reliability.
Table 3. CX74017 Recommended Operating Conditions Parameter
Power supply Operating junction temperature Operating ambient temperature
Minimum
2.7 -40 -40
Typical
3.0
Maximum
3.6 +100 +85
Units
V C C
Table 4. Power Consumption Specifications
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
Parameter
Total supply current: Rx mode, GSM Tx mode (no TIC VCO), GSM Synthesizer mode, GSM TIC VCO, GSM Rx mode, DCS/PCS Tx mode, DCS/PCS Synthesizer mode, DCS/PCS TIC VCO, DCS/PCS Sleep mode
Symbol
ICC
Test Condition
RXENA=SXENA=H TXENA=SXENA=H SXENA=H RXENA=SXENA=H TXENA=SXENA=H SXENA=H @ VCC = 3.6 V RXENA=TXENA= SXENA=L
Minimum
Typical
45 45 15 40 55 50 20 40
Maximum
Units
mA mA mA mA mA mA mA mA
20
A
Table 5. CX74017 Electrical Specifications - Receiver (1 of 4)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
Parameter
Input impedance Input operating frequency LNA Gain Voltage variation versus frequency Noise Figure
Symbol
ZIN Band 1 GLNA
Test Condition
LNA: EGSM With external match EGSM Rx band High Gain Mode Lowest Gain Mode Over band 1
Minimum
Typical
50
Maximum
Units

925 15 -3 *** TBD *** 2 9 3.5 -20
960
MHz dB dB dB dB dB dB dBm
NFMIN NFMAX NFBLOC
High gain mode Low gain mode With -25 dBm input blocker @ 10 MHz offset
Input 1 dB compression point
IP1dB
100950B
Conexant Proprietary
Preliminary Data Subject to Change
5 January 2, 2001
GSM RF Transceiver Table 5. CX74017 Electrical Specifications - Receiver (2 of 4)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
CX74017
Parameter
Input IP2 Mixer voltage gain Noise Figure Input 1 dB compression point
Symbol
IIP2 GMIX NF IP1dB
Test Condition
Mixer/LPF: EGSM Referred to LNA input High Gain Low Gain High Gain Low Gain In-band (high gain) In-band (low gain) @ 3 MHz
Minimum
65
Typical
Maximum
Units
dBm
40 22 13 23 -46 -26 -15 -6 -40 -30 -16 -8 1 -3 3 3 26 4.5 -45 -22 -23 LNA: DCS 50 1805 15 -3 *** TBD *** 3 10 4.5 -22 LNA: PCS 1990
dB dB dB dB dBV dBV dBV dBV dB dB dB dB dB degrees dB dB dB dBm dBm dBm  MHz dB dB dB dB dB dB dBm  1990 MHz dB dB dB dB dB dB
Output 1 dB compression point Blocker rejection
OP1dB @ 3 MHz offset @ 1.6 MHz offset @ 600 kHz offset @ 400 kHz offset
I/Q amplitude imbalance I/Q phase imbalance Combined LNA/mixer NF NFMIN NFMAX NFBLOC Combined input 1 dB compression point IP1dB High gain mode Low gain mode With -25 dBm input blocker @ 10 MHz offset In-band (high gain) In-band (low gain) @ 3 MHz Input impedance Input operating frequency LNA gain Voltage variation versus frequency Noise Figure NFMIN NFMAX NFBLOC Input 1 dB compression point Input impedance Input operating frequency LNA gain Voltage variation versus frequency Noise Figure NFMIN NFMAX NFBLOC IP1dB ZIN Band 2 GLNA With external match DCS/PCS Rx band High gain mode Lowest gain mode Over band 1 High gain mode Low gain mode With -28 dBm input blocker @ 10 MHz offset 1805 15 -3 *** TBD *** 3 10 4.5 ZIN Band 2 GLNA With external match DCS/PCS Rx band High gain mode Lowest gain mode Over band 1 High gain mode Low gain mode With -28 dBm input blocker @ 10 MHz offset
50
6 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017 Table 5. CX74017 Electrical Specifications - Receiver (3 of 4)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
GSM RF Transceiver
Parameter
Noise Figure
Symbol
NFMIN NFMAX NFBLOC
Test Condition
High gain mode Low gain mode With -28 dBm input blocker @ 10 MHz offset
Minimum
Typical
3 10 4.5 -22
Maximum
Units
dB dB dB dBm dBm
LNA: PCS (continued)
Input 1 dB compression point Input IP2 Mixer voltage gain Noise Figure Input 1 dB comp point
IP1dB Mixer/LPF: DCS/PCS IIP2 Gmix NF IP1dB Referred to LNA input High gain Low gain High gain Low gain In-band (high gain) In-band (low gain) @ 3 MHz 55
40 22 15 25 -46 -26 -15 -6 -40 -30 -16 -8 1 -3 3 4.2 28 5.7 -45 -22 -23 First Active LPF 10 -2 300 -6 4 -6 -13 -30 -42 2
dB dB dB dB dBV dBV dBV dBV dB dB dB dB dB degrees dB dB dB dBm dBm dBm dB dB kHz dBV dBV dB dB dB dB s ns dB/C
Output 1 dB compression point Blocker rejection
OP1dB @ 3 MHz offset @ 1.6 MHz offset @ 600 kHz offset @ 400 kHz offset
I/Q Amplitude imbalance I/Q Phase imbalance Combined LNA/mixer NF NFMIN NFMAX NFBLOC Combined input 1dB compression point IP1dB Highest gain mode Lowest gain mode With -28 dBm input blocker @ 10 MHz offset In-band (high gain) In-band (low gain) @ 3 MHz Gain Corner frequency Output 1 dB compression point Rejection AV FC OP1dB High gain Low gain @ 400 kHz @ 600 kHz @ 1.6 MHz @ 3 MHz Group delay Group delay variation Voltage gain temperature coefficient Combined with mixer Combined with mixer 50 *** TBD *** High gain Low gain
100950B
Conexant Proprietary
Preliminary Data Subject to Change
7 January 2, 2001
GSM RF Transceiver Table 5. CX74017 Electrical Specifications - Receiver (4 of 4)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
CX74017
Parameter
Gain: Highest gain Lowest gain Gain step Gain step accuracy Input 1 dB compression point Corner frequency (programmable) Corner frequency variation Rejection (FC=105 kHz) AV
Symbol
Test Condition
Second Active LPF
Minimum
Typical
Maximum
Units
40 0 dAV -0.5 IP1dB FC dFC Without calibration With calibration @200 kHz @400 kHz @600 kHz 50 -15 -7 -11 -34 -48 3 300 -6 150 +15 +7 2 0.5
dB dB dB dB dBV kHz % % dB dB dB s ns
Group delay Group delay variation
FC=105 kHz, (DC to 100 kHz) FC=105 kHz, (DC to 100 kHz) Second VGA AV
Voltage gain: Highest gain Lowest gain Gain step Differential output amplitude Output common mode voltage Output offset voltage Output impedance
30 0 6 AV = 30 dB AV = 0 dB 1.35 With DC offset correction ZOUT 200 5 2.5 0.1
dB dB dB V V V mV 
Table 6. CX74017 Electrical Specifications - Transmitter (1 of 2)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
Parameter
Differential input impedance Input signal level Input common mode voltage range Input offset voltage Input frequency 3 dB bandwidth Input common mode rejection ratio Output operating frequency Output impedance Output voltage Output noise power LO feedthrough Sideband suppression
Symbol
ZIN
Test Condition
I/Q Modulator
Minimum
Typical
20
Maximum
Units
k Vp-p
Differential VCM VOS 0.85
1 1.35 3 VCC - 1.3 5
V mV MHz dB
FIN = 100 kHz FIN = 1 MHz FOUT ZOUT VOUT NO @ 10 MHz offset @ 1.8 MHz offset 38 Per side -20 70
75 55 110 400 -15 -132 -130 -45 45 -128 -126 -40
MHz  dBV dBc/Hz dBc/Hz dBc dB
8 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017 Table 6. CX74017 Electrical Specifications - Transmitter (2 of 2)
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
GSM RF Transceiver
Parameter
Spurious
Symbol
Test Condition
Modulation 2nd order Modulation 3rd order Translational Loop
Minimum
Typical
-70 -60
Maximum
-40 -55 2000 110
Units
dBc dBc MHz MHz dBm // pF
I/Q Modulator (continued)
Transmit frequency (input from VCO) IF frequency Transmit input power Transmit input impedance Transmitter output phase noise
fTX fIF PIN ZIN NO @ 400 kHz offset @ 1.8 MHz offset With external 50  termination
800 70 -13 -10 300// 0.3
-7
-118 -124 2.0 1.5 .1.0 0.5 30 9 1 100 12 2 915 10 -153 -165 1710 6 8 -154 1850 6 8 -154 12 -150 -162 1785 10 -152 1910 10 -152
dBc/Hz dBc/Hz mA mA mA mA s
Translational Loop (continued) Charge pump output current: high impedance source/sink IOUT CP = state 4 CP = state 3 CP = state 2 CP = state 1 Device turn-on and lock time (with respect to enable input) N divide ratio range R divide ratio EGSM Translation Loop VCO Frequency range Power output Phase noise FRNG POUT NPH At 10 MHz offset At 20 MHz offset DCS Translation Loop VCO Frequency range Power output Phase noise Frequency range Power output Phase noise FRNG POUT NPH FRNG POUT NPH At 20 MHz offset At 20 MHz offset PCS Translation Loop VCO MHz dBm dBc/Hz MHz dBm dBc/Hz 880 8 MHz dBm dBc/Hz dBc/Hz
100950B
Conexant Proprietary
Preliminary Data Subject to Change
9 January 2, 2001
GSM RF Transceiver Table 7. CX74017 Electrical Specifications - Three-Wire Interface
(TA=25 C, VCC = 2.7 V unless otherwise noted) 
CX74017
Parameter
Data to clock setup time (see Figure 5) Data to clock hold time (see Figure 5) Clock pulse width High (see Figure 5) Clock pulse width Low (see Figure 5) Clock to load enable setup time see (Figure 5) Load enable pulse width (see Figure 5) LE falling edge to clock rising edge (see Figure 5) RXENA setup time TXENA setup time SXENA setup time FEENA setup time Power supply range Operating temperature range tCS
Symbol
tCH tCWH tCWL tES tEW tEFC
Test Condition
Min
50 10 50 50 50 50 50 50 50 50 50
Typical
Max
Units
ns ns ns ns ns ns ns ns ns ns ns
VCC TA
2.7 -40 25
3.6 85
V C
Table 8. CX74017 Electrical Specifications - Synthesizer (1 of 2)
(TA=25 C, VCCB = 2.7 V unless otherwise noted) 
Parameter
Operating input frequency Reference input frequency Phase detector frequency Input sensitivity Reference oscillator sensitivity In-band phase noise Spurious tones Charge pump output current (can be programmed in four steps)
Symbol
RF RF RF RF RF
Test Condition
Minimum
100 10 -15 0.5
Typical
13 13
Maximum
100 20
Units
MHz MHz MHz dBm
VDD -90 -75 100 200 300 400 0.1 5 10
VPEAK dBc/Hz dBc A A A A nA % %
RF, VCP = VDD/2 RF, VCP = VDD/2 RF, VCP = VDD/2 RF, VCP = VDD/2
Charge pump leakage current Charge pump sink versus source mismatch Charge pump current versus voltage/temperature Operating frequency Tuning voltage range Tuning sensitivity Phase noise KVCO FVCO
0.5 < VCP < VDD - 0.5 VCP = VDD/2 0.5 < VCP < VDD - 0.5 GSM LO 880 0.3
960 VCC - 0.5 20
@ 10 MHz offset @ 3 MHz offset @ 400 kHz offset
-144 -142 -125
10 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017 Table 8. CX74017 Electrical Specifications - Synthesizer (2 of 2)
(TA=25 C, VCCB = 2.7 V unless otherwise noted) 
GSM RF Transceiver
Parameter
Operating frequency Tuning voltage range Tuning sensitivity Phase noise
Symbol
FVCO
Test Condition
DCS/PCS LO
Minimum
1710 0.3
Typical
Maximum
1990 VCC - 0.5
Units
KVCO @ 10 MHz offset @ 3 MHz offset @ 400 kHz offset
20 -138 -136 -119
Table 9. CX74017 Operation Band Selection Logic BANDSEL1
0 0 1 1
BANDSEL2
0 1 0 1
Band of Operation
GSM900 GSM900 DCS1800 PCS1900
Table 10. Control And Output States (1 of 2) Symbol
EN LNA MIX LPF1 VGA2 Gain [2] [3] [4] V2 gain steps [7:5]
Function
Program mode enable bits [1:0]
Description
Logic 11 enables program mode Logic 1 selects the high gain mode of the LNA Logic 1 selects the high gain mode of the RX mixer Logic 1 selects the high gain mode of the active LPF s5 to s7 program the V2 gain in 6 dB increments: Logic 000 sets gain to 30 dB Logic 001 sets gain to 24 dB Logic 010 sets gain to 18 dB Logic 011 sets gain to 12 dB Logic 100 sets gain to 6 dB Logic 101 sets gain to 0 dB
AUX VGA1
[8] V1 gain steps [11:9]
Logic 1 activates 6 dB auxiliary gain S9 to s11 program the V1 gain in 6 dB increments: Logic 000 sets gain to 30 dB Logic 001 sets gain to 24 dB Logic 010 sets gain to 18 dB Logic 011 sets gain to 12 dB Logic 100 sets gain to 6 dB Logic 101 sets gain to 0 dB
VGA1
V1 fine tune[13:12]
S12 and s13 program V1 in 2 dB increments: Logic 00 sets gain to 0 dB Logic 01 sets gain to 2 dB Logic 10 sets gain to 4 dB
100950B
Conexant Proprietary
Preliminary Data Subject to Change
11 January 2, 2001
GSM RF Transceiver
CX74017
Table 10. Control And Output States (2 of 2)
Symbol
TXCP
Function
Tx charge pump bits[15:14]
Description
Two bit translation loop charge pump setting: Logic 00 sets TXCP to 0.5 mA Logic 01 sets TXCP to 1.0 mA Logic 10 sets TXCP to 1.5 mA Logic 11 sets TXCP to 2.0 mA
TXN
N divider [17:16]
These two bits set N divider ratio: Logic 00 sets N to 9 Logic 01 sets N to 10 Logic 10 sets N to 11 Logic 11 sets N to 12
TXR
R divider [18]
Set the R divider ratio selection: Logic 0 sets R to 1 Logic 1 sets R to 2.
TXPOL
CP polarity [19]
One bit CP polarity selection: Logic 0 sets POL to Normal Logic 1 sets POL to Inverted
RSVD RSVD RSVD RSVD
Reserved [20] Reserved [21] Reserved [22] Reserved [23]
Reserved bit Reserved bit Reserved bit Reserved bit
Table 11. Serial Interface Description for Fractional-N Sx
Symbol
D0 D1 EN EF SP SC LD
Function
Address bit [0] Address bit [1] Enable mode [2] Integer mode [3] Phase detector output polarity [4] Charge-pump output current [6:5] Test mode [8:7]
Description
Logic 0 enables three-wire programming for synthesizer Logic 0 enables PLL programming and logic 1 enables fractional-modulo programming Logic 0 enables synthesizer Logic 0 sets the integer-N mode and logic 1 sets the fractional-N mode Logic 0 sets the phase detector output for negative VCO gain and logic 1 sets it for positive VCO gain Charge pump current selection: (logic 00 sets 100 A, 01 = 200 A, 10 = 300 A, 11 = 400 A) Logic 00 multiplexes N divider output to LD output Logic 01 multiplexes R divider output to LD output Logic 10 multiplexes lock detect output to LD output
N R FN
Main divider [19:9] Reference divider [23:20] Fractional-N modulo [23:2]
Sets 11-bit main divider ratio with minimum division ratio of 64 Sets 4-bit reference divider ratio with minimum division ratio of 1 Sets fractional-N modulo up to 222 (= 4,194,300) modulo
12 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017
D23 RSVD D22 1 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 Aux Gain Select D7 D6 D5 D4
GSM RF Transceiver
D3 D2 D1 1 D0 1
RSVD
TXCP TXR TXN Divider TXCP Current VGA1 Fine Select Gain Select Polarity Divider Radio Select Select Ratio Select
VGA1 Coarse Gain Select
VGA2 Gain Select
Active Mixer LNA LPF1 Gain Gain Gain Select Select Select
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14 N DIVIDER
D13
D12
D11
D10
D9
D8 LD
D7
D6 SC
D5
D4 SP
D3 EF
D2 EN
D1 0 1
D0 0 0
R DIVIDER
Reserved for Fractional-N Programming
Figure 4. Programming Word Summary
DATA tCS CLOCK tCWH
S23
S22
S1
S0 tCH
tES tCWL tEW
LE
Figure 5. Serial Data Input Timing Diagram For Transceiver
C898
100950B
Conexant Proprietary
Preliminary Data Subject to Change
13 January 2, 2001
GSM RF Transceiver
4.436 9.00 - 0.10 Pin #1
CX74017
Solder Mask Pin #1
Exposed Metal R3.500
9.00 - 0.10 0.300 - 0.05 4.436
0.355 - 0.05 1.36 - 0.10 Mold Substrate 1.000 Typ
0.500
0.35 - 0.07
A ll d im e n s io n s a r e in m illim e te r s
C901
Figure 6. CX74017 64-Pin LGA Package Dimension Drawing
14 January 2, 2001
Conexant Proprietary
Preliminary Data Subject to Change
100950B
CX74017
GSM RF Transceiver
Ordering Information
Model Name
CX74017
Manufacturing Part Number
Product Revision
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100950B
Conexant Proprietary
Preliminary Data Subject to Change
15 January 2, 2001
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