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CX74016 CX74016

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CX74016	[] From old datasheet system

CX74016
RF/IF Transceiver For GSM Applications
Product Description
The CX74016 RF/IF Transceiver is a highly integrated, monolithic device optimized for use in Global System for Mobile Communications (GSM) and other Time Division Multiple Access (TDMA) single-band or multi-band applications. The receive path of the device consists of three Intermediate Frequency (IF) amplifiers with selectable gain, an I/Q demodulator, baseband filters, DC offset compensation circuitry, and selectable gain baseband amplifiers. The transmit path of the device consists of an In-Phase and Quadrature-Phase (I/Q) modulator and a frequency translation loop designed to perform frequency upconversion with high output spectral purity. The translation loop consists of a phase/frequency detector, a charge-pump, a mixer, and buffers for the required isolation between the RF section, Local Oscillator (LO), and IF inputs. In addition, the CX74016 features an on-chip dual-loop UHF/VHF frequency synthesizer circuit. It includes two sets of reference dividers, phase/frequency detectors, charge pumps, prescalers, main dividers, lock detector, and control circuits. The device package and pin configuration are shown in Figure 1. A block diagram of the CX74016 is shown in Figure 2. The signal pin assignments and functional pin descriptions are found in Table 1.
NC NC NC TXENA TXRFIN+ TXRFINVCC LO1IN LO1INR GND RXIFIN+
Features
* Quadrature demodulator for downconversion * 80 dB IF gain range and 30 dB baseband gain range * Integrated receive baseband filters with tunable bandwidth * Integrated transmit path with high phase accuracy * Reduced filtering requirements for the transmit path * Broad RF and IF range for multi-band operation * Integrated selectable local oscillator dividers/phase shifters and high/low-side injection for frequency plan flexibility * On-chip second local oscillator * Includes fully programmable dual-loop synthesizer * Selectable charge pump currents for both synthesizers * Digital lock detector * Separate enable lines for transmit, receive, and synthesizer modes for power management * 72-pin Land Grid Array (LGA) 10 mm x 10 mm package
Applications
* GSM900/DCS1800/PCS1900 digital cellular telephony * Multi-mode, multi-band terminals
RXIFINRXENA
61 60
72
71
70
69
68
67
66
65
64
63
62
59
58
57
NC GND TLCPO VCC VCC VCC GND TXIFIN+ TXIFINGND TXI+ TXINC TXQ+ TXQNC TXMO+ TXMONC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
56
LE CLK NC NC
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
NC NC RXI+ RXIRXQ+ RXQTH CTH1 CTH2 VCC UCPO GND FREF GND VCPO VCC LD
36
19
37
NC DATA RXIFF+ RXIFFSXENA BPC GND VCC RES2 RES1 VCC GND LPFADJ VCC NC NC NC NC NC
C870
Figure 1. CX74016 Pin Configuration - 72-Pin LGA
Data Sheet
Conexant - Preliminary
Proprietary Information
Doc. No. 100778A July 25, 2000
CX74016
RF/IF Transceiver
RXIFF+
RXIFF-
LPFADJ
+20 dB 0 dB
+20 dB +18 dB -10 dB
+20 dB +18 dB -10 dB
PGD 0/10/20/30 dB RXI+ RXIDC OC 90 CTH1 CTH2 T/H RXQ+ RXQ-
PGA
RXIF+ RXIF-
PGB
PGC
/2
RX LO2
/4
Rx Sx
Aux Synthesizer
RES1 RES2 BPC 3-Wire LO1IN+ LO1IN-
Rx Sx
VCPO FREF Bias RXENA TXENA SXENA LD CLK DATA LE UCPO
/2
SX LO2
/4
Main Synthesizer
Control
Tx
/2
TX LO2
/4
Tx
TXI+
TXRFIN+ TXRFIN-
/1
TXI-
/2
TLCPO
CHP
PFD
/1
/2
90
TXQ+ TXQ-
TXIFIN-
TXIFIN+
TXMO+ TXMO-
C019
Figure 2. CX74016 Block Diagram
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100778A July 25, 2000
RF/IF Transceiver Table 1. CX74016 Signal Description Pin #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
CX74016
Name
NC GND TLCPO VCC VCC VCC GND TXIFIN+ TXIFIN- GND TXI+ TXI- NC TXQ+ TXQ- NC TXMO+ TXMO- NC NC NC RXI+ RXI- RXQ+ RXQ- TH CTH1 CTH2 VCC UCPO GND FREF GND VCPO VCC LD No connect
Description
Ground for translational loop Translation loop charge pump output Supply for translation loop Supply Supply Ground for Tx IF and baseband Tx IF positive input Tx IF negative input Ground Tx modulator positive input Tx modulator negative input No connect Tx modulator positive input Tx modulator negative input No connect Tx modulator positive output Tx modulator negative output No connect No connect No connect Rx baseband positive output Rx baseband negative output Rx baseband positive output Rx baseband negative output Track and hold signal Capacitor for track and hold Capacitor for track and hold Supply for UHF loop UHF charge pump output (main synthesizer) Ground Synthesizer reference frequency input Ground VHF charge pump output Supply for VHF loop Lock detect output
Pin #
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
Name
NC NC NC NC NC VCC LPFADJ GND VCC RES1 RES2 VCC GND BPC SXENA RXIFF- RXIFF+ DATA NC NC NC CLK LE RXENA RXIFIN- RXIFIN+ GND LO1INR LO1IN VCC TXRFIN- TXRFIN+ TXENA NC NC NC No connect No connect No connect No connect No connect Supply
Description
Adjustment pin for baseband low pass filter corner frequency Ground Supply for oscillator Resonator pin Resonator pin Supply for oscillator Ground for oscillator Bypass capacitor Synthesizer enable Rx IF filter pin Rx IF filter pin Serial data input No connect No connect No connect Serial clock input Latch enable for serial data Receiver enable Rx IF input Rx IF input Ground for translation loop mixer and Rx IF section 1st local oscillator input reference 1st local oscillator input Supply for translation loop mixer and Rx IF section Transmit RF negative input reference Transmit RF positive input Transmit enable No connect No connect No connect
100778A July 25, 2000
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CX74016
RF/IF Transceiver
Technical Description
The CX74016 RF/IF transceiver is comprised of a receive path, a transmit path, and a synthesizer section as shown in Figure 2. The receive path consists of a selectable gain IF chain, a quadrature demodulator, and baseband amplifier circuitry with I and Q outputs. The transmit path is essentially an I/Q modulator with a translation loop for frequency up-conversion. An on-chip oscillator and a dual-loop UHF/VHF frequency synthesizer circuit make up the synthesizer section. Each section of the CX74016 is separately enabled via the enable signals TXENA, RXENA, and SXENA. The block diagram in Figure 3 shows a complete RF/IF dualband transceiver chipset using the CX74016. Receive Path _______________________________________ Selectable Gain IF Chain and Quadrature Mixer. The receive path of the CX74016 is composed of an IF section and a baseband section. The IF section consists of three programmable gain amplifiers: PGA, PGB, and PGC. PGA has two gain settings, either 0 dB or 20 dB. Both PGB and PGC have a gain range of -10 dB to 20 dB, programmable in 2 dB steps. The output of PGC is fed to a quadrature mixer. The LO inputs to the quadrature mixer are taken from the outputs of a quadrature divider (divide by 2 or 4).
Baseband Integrated Filters, Baseband Amplifiers, and DC Offset Compensation. Immediately following the quadrature mixer (demodulator) is the baseband section (DC offset compensation circuitry, two integrated baseband filters, and two programmable gain amplifiers). Each programmable gain amplifier in the baseband section, both labelled PGD, has four different gain settings: 0 dB, 10 dB, 20 dB, or 30 dB. The corner frequency of the integrated baseband filters is adjustable by using an appropriate value resistor at pin 43, LPFADJ. At the nominal cutoff frequency of 105 kHz, the resistor value is 75.1 k. Due to possible high gain of the baseband amplifiers (PGD), any DC offsets at the outputs of the quadrature mixer are amplified and, if uncorrected, the I and Q outputs can suffer from significant unwanted DC offset voltages. To cancel out these effects, the CX74016 must be calibrated. During compensation, the correction voltages are stored in external hold capacitors, CTH1 and CTH2, and then the loop is opened immediately thereafter. The corrected I and Q outputs are then fed directly to external circuitry for further baseband processing.
GSM Rx Filter
RF212
LC Tank
CX74016
RXI
PGD
IF SAW Filter
CTH1 CTH2
PGA
DC OC
T/H RXQ
90
PGB
DCS Rx Filter Tx/Rx VCO
PGC
PGD
Bias
/2 /4 /2 /2 /4
Tank UHF VCO
/4
Aux SX 3-Wire Control Main SX
SX ENA RX ENA TX ENA VCPO FREF DATA CLK LE LD
UCPO Tx/Rx VCO
Combiner
/1 /2
LPF
TXI
Antenna CHP PFD
/1 /2
90
Tx DCS VCO
T/R Coupler
VAPC
LPF
TXQ
Diplexer
RF142
T/R
LOOP FILTER
TX IF Filter
Tx GSM VCO
C025
RM008
Figure 3. Typical Dual-Band Transceiver Application Block Diagram Using the CX74016
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100778A July 25, 2000
RF/IF Transceiver
CX74016
TDMA slots
Rx slot
RXENA
T1 T2
T/H
T3 T4
Front-end enable (external to CX74016)
C026
Figure 4. CX74016 Sample and Hold Timing Diagram
Table 2. Minimum Required DC Offset Calibration Time T2 and Droop Rate Hold Capacitor (CTH1, CTH2)
Cold start Frame-to-frame Typical droop-rate (@ I/Q outputs)
22 nF
60  sec 10  sec 1 mV/msec
120 nF
350  sec 60  sec 0.17 mV/msec
The timing diagram for this calibration sequence in reference to the receive slot is shown in Figure 4 (the front-end mixer is assumed to be Conexant's RF212 dual-band, image reject downconverter). At first, the CX74016 receiver is turned on (RXENA is high). After time T1, the track and hold signal, T/H, places the DC compensation circuitry in the track mode for time T2. Then there is a settling time, T3, before the external frontend is turned on. Finally, the front-end must be turned on for time T4 before the receive slot. Time T2 can vary from 10 sec to 350 sec. This duration is dependent on the value of the hold capacitors (CTH1 and
CTH2), and whether the calibration is done from frame to frame or from a cold start. This is tabulated in Table 2. Because of on-chip loading currents, the hold capacitors (CTH1 and CTH2) slowly discharge causing the I and Q DC offset voltages to droop if the CX74016 remains uncalibrated for an extended period of time (the droop rate versus the hold capacitor is also shown in Table 2). To rectify this voltage droop, it is recommended that recalibration occur before every receive slot (i.e., every 4.6 msec for GSM).
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CX74016
RF/IF Transceiver
VCC
Vtune
External Resonator
RES1 (pin 46)
RES2 (pin 47)
CX74016
C027
Figure 5. CX74016 Internal VCO
Synthesizer Section _________________________________ Frequency Synthesizer. There are two frequency synthesizers on the chip, one primary and one auxiliary. The primary synthesizer provides frequencies from 500 MHz to 2 GHz. It consists of a 32/33 modulus prescaler, a 13-bit R counter, an 18-bit N counter, a phase detector with lock detection, and a charge pump. The auxiliary synthesizer, with frequency range from 50 MHz to 450 MHz, consists of an 8/9 modulus prescaler, a 13-bit R counter, a 16-bit N counter, a phase detector with lock detection, and a charge pump. Each synthesizer has four charge pump current settings for optimal performance. On-Chip Oscillator with External Resonant Circuit. The onchip VCO uses a fully differential architecture. This architecture inherently provides low even order harmonics, minimizing the phase variation of the phase shifters used to generate quadrature local oscillator signals. The architecture also provides better power supply rejection as well as superior immunity to common mode radiation as compared to singleended designs. The immunity of the resonators minimizes the effect of pulling of the center frequency of the VCO due to the presence of a large signal in its spectral proximity. The on-chip oscillator together with a few external components as resonant elements, form a VHF Voltage-Controlled Oscillator (VCO) (Figure 5 shows the VCO configuration). The differential VCO output is buffered and then fed to three dividers (Rx, Tx, and Sx). Each of the dividers have a selectable divide ratio of
6
either 2 or 4. The Rx and Tx dividers are both quadrature dividers that generate in-phase and quadrature-phase LOs. The on-chip oscillator, with the on-chip auxiliary synthesizer, provides a complete VHF frequency synthesis for the Rx VHF LO and Tx VHF LO. Three-Wire Bus Control Interface. The three-wire bus control allows the CX74016 to be optimized for any desired frequency plan. It also programs the two on-chip frequency synthesizers. To ensure that the data remains latched, one of the signals (TXENA, RXENA, or SXENA) must stay enabled. When bit C0 is set to 1, it allows for divider selections in the translation loop, high-side/low-side injection for the image reject mixer, and the receive IF amplifiers' gain setting. When bit C0 is set to 0, it programs the primary/auxiliary synthesizer, the R/N counter, charge pump polarity, charge pump output current, and prescaler setting. Transmit Path _______________________________________ I/Q Modulator With IF Output Amplifier. The inputs to the I/Q modulator are differential I and Q baseband signals which are low-pass filtered and then applied to a pair of double-balanced mixers (see Figure 2). The outputs of the mixers are combined to produce a modulated signal which is then filtered externally and input through pins 8 and 9 (TXIFIN+ and TXIFIN-) to the reference divider in the translation loop.
100778A July 25, 2000
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RF/IF Transceiver
CX74016
Translation Loop Circuit. The translation loop circuit consists of a phase and frequency detector, a charge pump, a Tx RF input buffer, an LO input buffer, a mixer, two dividers, and a low pass filter. The translation loop circuit, together with the external transmit VCO, external LO, and loop filter, form a Phase Locked Loop (PLL) with a mixer in the feedback loop. This PLL upconverts the modulated IF signal to the transmit frequency which then drives the final power amplifier. Since inherent bandpass filtering occurs in the PLL, the need for a post-Power Amplifier (PA) duplexer is removed. This is the major advantage a translation loop approach has over the conventional upconversion scheme. The elimination of this duplexer reduces the loss in the transmit path which, in turn, reduces the required output level required from the final PA and, therefore, reduces the current consumption. Immediate benefits of this approach are increased handset talk time and standby time, and less component count. The charge pump current can be programmed to be either 1 mA or 0.5 mA and the translation loop can also be programmed to allow for high side or low side injection of the first LO input with respect to the transmit RF. Even greater flexibility in the transceiver frequency planning is possible because of the programmable dividers in the feedback and the reference paths.
Electrical and Mechanical Specifications ________________ The absolute maximum ratings of the CX74016 are provided in Table 3, and the electrical specifications are provided in Table 4. Table 5, Table 6, and Table 7 detail the setting of the programmable operation modes. Figure 6 illustrates the timing of the three-wire bus control signal. Figure 7 shows the 1 dB compression point graphs for the receiver. Figure 8 provides the package dimensions for the 72-pin device. The CX74016 device has four metal ground paddles on the bottom of the LGA package. These paddles must be soldered to ground on the PCB. The PCB footprint design and soldering guidelines are described in the Conexant Application Note, "RF Land Grid Array Layout and Soldering Guidelines" (document #W205).
ESD Sensitivity
The CX74016 is a static-sensitive electronic device. Do not operate or store near strong electrostatic fields. Take proper ESD precautions.
Table 3. Absolute Maximum Ratings Parameter
Ambient Operating Temperature Storage Temperature Power Dissipation Supply Voltage (VCC) Input Voltage Range 0 GND
Minimum
-30 -50
Maximum
+85 +125 600 4.5 VCC
Unit
C C mW V V
100778A July 25, 2000
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CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (1 of 5)
(TA = 25 C, VCC = 3.0 V, except where specified)
Parameter
Input impedance for the RXIF+ and RXIF- pins Input operating frequency Voltage gain AV AV Gain step (Note 1) Gain step accuracy (Note 2) Single-sideband noise figure Input 1 dB compression point (Note 3)
Symbol
ZIN FIN
Test Condition
Differential
Min
Typical
500// 0.3
Max
Units
 pF
Receive IF Path
70 FIN = 400 MHz: High gain mode Low gain mode 57 -23 60 -20 2 -0.5
450 63 -17
MHz dB dB dB
dAV
+0.5 7 23 -75 -12 300// 2
dB dB dB dBV dBV  pF
NF NF P1dB P1dB
High gain mode Low gain mode High gain mode (60 dB) Low gain mode (-20 dB) Differential I/Q Demodulator
IF filter pin impedance for the RXIFF+ and RXIFF- pins
ZIF
I/Q amplitude imbalance I/Q phase imbalance Noise figure Output 1 dB compression point Baseband Filter Corner frequency (programmable) Corner frequency variation Rejection FC dFC FC = 105 kHz: @200 kHz @400 kHz @600 kHz FC = 105 kHz: DC to 100 kHz FC = 105 kHz: DC to 100 kHz 50 -15 8 30 40 3 300 NF -4.5 15 -2
1 +4.5
dB degrees dB dBV
150 +15
kHz % dB dB dB
26
Group delay Group delay variation
5 500
sec nsec
8
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100778A July 25, 2000
RF/IF Transceiver
CX74016
Table 4. CX74016 Electrical Specifications (2 of 5)
(TA = 25 C, VCC = 3.0 V, except where specified)
Parameter
Voltage gain AV
Symbol
Test Condition
Min
Typical
0 10 20 30
Max
Units
dB dB dB dB
Baseband Amplifier
Output amplitude
AV = 30 dB AV = 20 dB AV = 10 dB AV = 0 dB 1.35 With DC offset compensation Without DC offset compensation and AV = 0 dB
2.5 1.8 1.0 0.4
Vp-p Vp-p Vp-p Vp-p V
Output common mode voltage Output offset voltage
5
mV
100
mV mV/ msec 
Output voltage droop/rise rate
With DC offset compensation and CTH = 22 nF ZOUT Differential I/Q Modulator
1 200
Output impedance
Input impedance Input signal level Input common mode voltage range Input offset voltage Input frequency 3 dB bandwidth Input common mode rejection ratio Output operating frequency Output impedance Output voltage Output noise power LO feedthrough Sideband suppression Spurious (Note 4)
ZIN
Differential @ 100 kHz Differential
20 1 0.85 1.35 1 10 VCC - 1.35 5
k Vp-p V mV MHz dB dB 425 MHz //pF dBV -126 -40 dBc/Hz dBc dBc -40 -45 dBc dBc
VCM VOS
FIN = 100 kHz FIN = 1 MHz FOUT ZOUT VOUT NO 10 MHz offset Differential @ 400 MHz -20 70
75 55
400// 3.1 -15 -130 -45 40 50 -70 -60
@ 200 kHz offset @ 300 kHz offset
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CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (3 of 5) (TA = 25 C, VCC = 3.0 V, except where specified) Parameter
Transmit frequency (input from VCO) LO input frequency IF frequency Transmit input power Transmit input impedance (at pin 68) LO input power with external 50  termination LO input impedance (at pin 65) Charge-pump output current fTX fLO fIF fIF PIN ZIN PIN ZIN IOUT With pin 64 AC grounded source/sink (CPOI=HIGH) source/sink (CPOI=LOW) high impedance With divide-by-2 With divide-by-1 With external 50  termination With pin 67 AC grounded -13
Symbol
Test Condition
Min
800 800 70 70 -13
Typical
Max
2000 2000 425 300
Units
MHz MHz MHz MHz dBm  pF
Translation Loop
-10 300// 0.3 -10 300// 0.3 1.0 0.5 0.02
-7
-7
dBm  pF mA mA mA dBc dBc dBc dBc
Transmit output zero crossing spurs (Note 5): 2X spurs 3X spurs 4X spurs 5X spurs Transmit output noise level (Note 5) Device turn-on and lock time (with respect to enable input) VCO Operating frequency set by resonator Tuning voltage range FVCO Varactor ground referenced Varactor supply referenced Resonator pin impedance Tuning sensitivity (Note 6) Phase noise (Note 6) KVCO Differential FVCO = 800 MHz FVCO = 800 MHz, 400 kHz offset, resonator Q = 20 At 20 MHz offset from carrier 1 MHz loop bandwidth
-62
-65 -70 -70 -70 -165 30 -162 100
dBc/Hz sec MHz V
300 0.3
900
VCC - 0.3 10k// 0.4 50 -122
V  pF MHz/V dBc/Hz
10
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100778A July 25, 2000
RF/IF Transceiver
CX74016
Table 4. CX74016 Electrical Specifications (4 of 5)
(TA = 25 C, VCC = 3.0 V, except where specified)
Parameter
Input frequency (low frequency mode), Auxiliary PLL Input frequency (high frequency mode), Auxiliary PLL Input frequency (low frequency mode), Primary PLL Input frequency (high frequency mode), Primary PLL Reference frequency Reference input sensitivity Phase detector frequency Charge pump output impedance Prescaler input sensitivity Prescaler input impedance PLL contribution to phase jitter (N=5835)
Symbol
Synthesizer fINL(IF) fINH(IF) fINL(RF) fINH(RF) fREF RIN fPD ZO PIN ZIN NMAIN
Test Condition
Min
100 250 500 500 1 500 10
Typical
Max
260 450 1200 2000 40
Units
MHz MHz MHz MHz MHz mVpp
10000 10
kHz M mVpp  degrees RMS
100 @ 1 GHz Primary only; Fcomparison = 200 kHz, 10 kHz loop BW; integrated from 200 to 270,000 Hz Aux only; Fcomparison = 300 kHz, 10 kHz loop BW; integrated from 200 to 270,000 Hz t = 25 C t = 25 C t = 25 C t = 25 C t = 25 C t = 25 C t = 25 C t = 25 C 0.6 0.9 1.35 2.02 0.4 0.6 0.9 1.35 40 100 1.2
PLL contribution to phase jitter (N=1680)
NAUX
0.75
degrees RMS
Primary charge pump current, step 0 Primary charge pump current, step 1 Primary charge pump current, step 2 Primary charge pump current, step 3 Auxiliary charge pump current, step 0 Auxiliary charge pump current, step 1 Auxiliary charge pump current, step 2 Auxiliary charge pump current, step 3 Charge pump current relative step size (current change from any one step to next step in sequence) Charge pump leakage current Charge pump output voltage compliance Lock detect time constant
IDOR,0 IDOR,1 IDOR,2 IDOR,3 IDOI,0 IDOI,1 IDOI,2 IDOI,3 IDOS IDOO VDO tLOCK
0.8 1.2 1.8 2.7 0.5 0.8 1.2 1.8 50 0.1
1.0 1.5 2.25 3.38 0.67 1.0 1.5 2.25 60
mA mA mA mA mA mA mA mA % nA
0.5 500
VCC - 0.5
V sec
100778A July 25, 2000
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CX74016
RF/IF Transceiver
Table 4. CX74016 Electrical Specifications (5 of 5)
(TA = 25 C, VCC = 3.0 V, except where specified)
Parameter
DC offset calibration timing (see Figure 4): T1 T2 (see Table 2) T3 T4 (assuming RF212 front-end mixer) Enable and control VIH Enable and control VIL Enable and control IIH Enable and control IIL Total supply current (Note 7): Rx mode Tx mode Synthesizer mode Power supply range Operating temperature range
Symbol
Transceiver
Test Condition
Min
Typical
Max
Units
40 5 20 VIH VIL IIH IIL ICC SXENA = RXENA = on SXENA = TXENA = on SXENA = on 63 64 28 VCC TA 3-Wire Control 2.7 -30 3.0 +25 3.6 +85 -10 20 -1 0.8 x VCC 0.2 x VCC 60 0
sec sec sec sec V V A A mA mA mA V C nsec nsec nsec nsec nsec nsec nsec
Data to clock setup time (Note 8) Data to clock hold time (Note 8) Clock pulse width high (Note 8) Clock pulse width low (Note 8) Clock to load enable setup time (Note 8) Load enable pulse width (Note 8) Load enable transition to clock start time
tCS tCH tCWH tCWL tES tEW tLS
50 10 50 50 50 50 50
Note 1: Gain steps are such that monotonicity is maintained throughout the entire IF gain range. Note 2: Specified down to 2.8 V supply voltage. Slight degradation at temperature extremes for 2.7 V supply voltage. Note 3: Refer to Figure 7 for the 1 dB compression point of the entire receiver chain, including the baseband gain section. Note 4: For 1 Vp-p 100 kHz differential signals across lIN and QIN. Note 5: Using transmit VCO with similar characteristics as Murata MQE 550-902. Note 6: Using varactors with similar characteristics as Alpha part SMV1234-004. Note 7: The total voltage supply current for the Rx, Tx, and synthesizer modes increases by 1 mA if the VHF LO buffer is on. Note 8: Refer to Figure 6.
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RF/IF Transceiver
CX74016
Table 5. CX74016. Control Bits and Output States (1 of 2) Block
LO 1
C0
Bit
S1 S2 S3
Function
RX LO /2//4 SX LO2 /2//4 TX LO /2//4 TX IF /1//2 TX MIX OUT /1//2 TX LO Injection CP Output Current RX PGA1 RX PGB1 RX PGB2 RX PGB3 RX PGB4 RX PGC1 RX PGC2 RX PGC3 RX PGC4 RX PGD1 RX PGD2 Reserved Reserved VHF LO BUF VHF Prescaler UHF Prescaler
Description
Selects the division ratio for RX LO2 (0 = division ratio is 2; 1 = division ratio is 4) Selects the division ratio for SX LO2 (0 = division ratio is 2; 1 = division ratio is 4) Selects the division ratio for TX LO2 (0 = division ratio is 2; 1 = division ratio is 4) Selects the division ratio for TX IF (0 = division ratio is 1; 1 = division ratio is 2) Selects the division ratio for TX MIX output signal (0 = division ratio is 1; 1 = division ratio is 2) Selects between high- and low-side injection of first LO input with respect to transmit RF (0 = low side, 1 = high side) Selects the TL loop CP output current (0 = output current is 0.5 mA; 1 = output current is 1 mA)
TX
1
S4 S5 S6 S7
Receive
1
S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S!8 S19 S20 S21 S22 S23
Selects the RX IF/baseband gain (see Tables 6 and 7)
TRX
1
S19 bit may be programmed as "don't care." S20 bit may be programmed as "don't care." Selects the state of the LO buffer (1 = LO buffer on; 0 = LO buffer off). Needs to be "1" for correct operation. Select the state of the VHF prescaler (1 = on, 0 = off). Select the state of the UHF prescaler (1 = on, 0 = off). Set to "1" for normal operation.
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CX74016
RF/IF Transceiver
Table 5. CX74016. Control Bits and Output States (2 of 2) Block
SX 0
C0
Bit
S1 S2 R/N
Function
IF/RF
Description
Selects one of the synthesizers, either the Auxiliary or Primary (1 = primary; 0 = auxiliary) Selects the R counter or N counter register within the synthesizer. The N counter register also controls the phaser detector current and inversion (or phase comparison reference signal) (0 = N counter register; 1 = R counter register) Determines the maximum input frequency at which the prescaler will operate: S1 = 1 S1 = 0 Primary: 0 = 1.2 GHz, 1 = 2.0 GHz Auxiliary: 0 = 260 MHz, 1 = 450 MHz
S3
S2 = 0: Prescaler frequency response S2 = 1: Output invert
Controls polarity of charge pump output (0 = normal operation; 1 = inverted) Powers down the synthesizers. Only the synthesizer indicated by S1 is affected (0 = normal operation; 1 = power down) Used to inhibit lock detect/test output (0 = lock detect/test output enable; 1 = lock detect/test output disable) This 18-bit value is loaded into the N counter latch. This value sets the cascaded division ratio of the prescaler and N counter (S22 = MSB, S5 = LSB). For the auxiliary N divider (16-bit), bits S21 and S22 are "don't care." The least significant bits (S5-S9 for primary N divider; S5-S7 for auxiliary N divider) set the prescaler counter.
S4
S2 = 0: Synth. power down S 2= 1: Test mode inhibit
S5 to S22
S2 = 0: N counter
S5S6
S2 = 1: Output current
These bits set the charge pump output current: S1 = 1 S1 = 0 Primary: Auxiliary: 00 = 0.8, 01 = 1.2, 10 = 1.8, 11 = 2.7 [mA] 00 = 0.5, 01 = 0.8, 10 = 1.2, 11 = 1.8 [mA]
S7 S8S9
S2 = 1: CP high impedance S2 = 1: Test mode
Charge pump output. Only the charge pump output selected by the S1 bit is affected (0 = normal operation; 1 = high impedance) These bits select which signal to output at the lock detect/test pin (pin 36): 00 = (Lock detect of Aux) AND (lock detect of Primary) 01 = Output of R divider 10 = Output of N divider 11 = Output of lock detect Aux (S1=0) or Primary (S1=1) These 13 bits set the reference divider value (S22 = MSB, S10 = LSB).
S10S22
S2 = 1: R counter
Table 6. Receive Baseband Gain Gain (dB)
30 20 10 0
PGD 1
1 1 0 0
2
1 0 1 0
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RF/IF Transceiver
CX74016
Table 7. Receive IF Gain Gain (dB)
60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20
PGA 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0
PGB 1
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0
PGC 3
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0
Gain 3
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
PGA 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGB 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PGC 3
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
2
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1
4
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(dB)
18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20
2
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
2
1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
3
1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
4
1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
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CX74016
RF/IF Transceiver
Data tCS
S22/S23
S20
S1
C0
t CH
Clock
tCWH tCWL tLS
tES tEW
LE
C028
Figure 6. CX74016 Timing Diagram
-10 -20 -30 -40 -50 -60 -70 -80 -90 80 60 40 20 0 -20
PGD Gain Setting
Input Compression (dBV)
Overall Rx Gain @ IF = 400 MHz (dB)
0dB 10dB 20dB 30dB
C903
Figure 7. Receiver Input Compression Graph
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RF/IF Transceiver
CX74016
4.935 10.00  0.10
Solder Mask
Pin #1
Pin #1
Exposed Metal
0.500
R3.600 10.00  0.10 0.300  0.05
4.936
0.355  0.05 1.000 Typ 1.36  0.10 0.35  0.05
0.500
All dimensions are in millimeters
C865
Figure 8. CX74016 Package Dimensions - 72-Pin LGA
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CX74016
RF/IF Transceiver
Ordering Information
Model Name
CX74016
Manufacturing Part Number
CX74016
Product Revision
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