View HM17CM4096_4105981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HM17CM4096
Preliminary Specification
128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM
s INSTRUCTION HM17CM4096 is a dot-Matrix LCD drive IC with 162 commons and 384 segments (128 X RGB) drive ports for 4,096 colors driving. This IC stores the serial or parallel BIT data transferred by the microcomputer on the built-in RAM (248,832 bits for graphic) and generates the signals to drive LCD panel. Color graphic display is achieved by selecting 16 gray (16R 16G 16B = 4,096 color or 256 color mode ) levels out of 32 gray palettes independently. This IC is suitable for battery-operated system, hand-carrying information equipment by ensuring low power consumption, low power supply (1.7V ~ ) and a wide range of operating voltage. And 162 x 128 display is possible with just one chip.

EXTERNAL SHAPE
|
HM17CM4096
s FEATURES
4,096 color bitmap LCD driver LCD drive outputs 128xRGB segments, 162 commons for graphic Display RAM capacity 248,832 bits (for graphic usage) Gradation display 16 gradations can be selected from 32 gradations by PWM control Black/White display 162 (128 3) bits display is possible 8 bit BUS interface directly connectable with 68 / 80 series CPU RAM data length 8 BIT / 16 BIT selectable Serial interface available 3 or 4 line interface is selectable Programmable duty / bias ratio with command Various instruction set display data read/write, display ON/OFF, positive/negative display, page address set display start line address set, partial display, bias select, column address set, all display ON/OFF, boosting selection, n line inversion mode read modified write, power save ... Built-in voltage booster (programmable) : 7 boosting Built-in voltage regulator Controllable contrast with built-in electric volume (128 steps) Low current consumption Logic supply 1.7V ~ 3.3V LCD drive supply 5.0V ~ 18.0V C-MOS silicon process
Package

TCP/ bumped chip / bare chip and so on
01/07/06
-1-
HM17CM4096
PAD LAYOUT
SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 COM81 COM82 COM83 COM84 COM96 COM97 COM98 COM99 COM100 DMY113
DMY114 COM101 COM102
COM148 COM149 DMY115
1
note 1) The (L) (R) (C) mark after port name is internally shorted. note 2) DMYport is opened electrically.

chip thickness bump size bump pitch bump height bump material
chip center chip size
COM151 COM150 DMY0
DMY7 DMY6 DMY5 DMY4 DMY3 VSSA(R) VSSA(C) VSSA(L) DMY2 DMY1 COMI161 COM160
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4/SPOL D3/SMODE D2/EXCS D1/SDA
: X= 0m, Y= 0m : with scribe lane : 19.84 2.97mm , main chip : 19.83mm 2.96mm : 525m 25m : 68m 33m, 68m 80m : 45m(Min) : 18 3m : Au
-2-
HM17CM4096
DMY3(R) DMY3(L) COM21
DMY4(L) DMY4(R) COM20 COM19 COM18 COM17 COM80
COM69 DMY2(R) DMY2(L)
DMY1(R) DMY1(L) COM70
COM3 COM2 COM1 COM0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2
C6-(R) C6-(L) C6+(R) C6+(L) C5-(R) C5-(L) C5+(R) C5+(L) C4-(R) C4-(L) C4+(R) C4+(L) C3-(R) C3-(L) C3+(R) C3+(L) C2-(R) C2-(L) C2+(R) C2+(L) C1-(R) C1-(L) C1+(R)
a
a
c
d
d
align mark appearance and size
b
VLCD(R) VLCD(L) VSSH(C)
Y
OSC2
coordinates of align marks
X
(X= TBD m, Y= TBD m) (X= TBD m, Y= TBD m)
a : 30m b : 6m c : 120m d : 27m
b
c
-3-
HM17CM4096
s PAD coordinates 1
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin name DMY0 COM150 COM151 COM152 COM153 COM154 COM155 COM156 COM157 COM158 COM159 COM160 COM161 DMY1 DMY2 VSSA(L) VSSA(C) VSSA(R) DMY3 DMY4 DMY5 DMY6 DMY7 TEST1 DMY8 DMY9 DMY10 DMY11 DMY12 VDD(L) VDD(C) VDD(R) DMY13 DMY14 DMY15 DMY16 DMY17 DMY18 RESB DMY19 DMY20 DMY21 CSB DMY22 DMY23 DMY24 RS DMY25 DMY26 VSS(L) VSS(C) X(m) -9581 -9518 -9473 -9428 -9383 -9338 -9293 -9248 -9203 -9158 -9113 -9068 -9023 -8910 -8850 -8790 -8730 -8670 -8610 -8550 -8490 -8430 -8370 -8310 -8250 -8190 -8130 -8070 -8010 -7950 -7890 -7830 -7650 -7590 -7530 -7470 -7410 -7350 -7290 -7230 -7170 -7110 -7050 -6990 -6930 -6870 -6810 -6750 -6690 -6630 -6570 Y(m) -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 PAD No. 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 Pin name VSS(R) DMY27 DMY28 TEST2 DMY29 DMY30 VDDA(L) VDDA(C) VDDA(R) DMY31 DMY32 P/S DMY33 DMY34 DMY35 SEL68 DMY36 DMY37 VSSA(L) VSSA(C) VSSA(R) DMY38 DMY39 WRB DMY40 DMY41 DMY42 RDB DMY43 DMY44 DMY45 VDD(L) VDD(C) VDD(R) DMY46 DMY47 D0 DMY48 D1 DMY49 D2 DMY50 D3 DMY51 D4 DMY52 D5 DMY53 D6 DMY54 D7 X (m) Y (m) -6510 -6330 -6270 -6210 -6150 -6090 -6030 -5970 -5910 -5850 -5790 -5730 -5670 -5610 -5550 -5490 -5430 -5370 -5310 -5250 -5190 -5130 -5070 -5010 -4950 -4890 -4830 -4770 -4710 -4650 -4590 -4530 -4470 -4410 -4230 -4170 -4050 -3930 -3810 -3690 -3570 -3450 -3330 -3210 -3090 -2970 -2850 -2730 -2610 -2490 -2370 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396

chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) No. 103 DMY55 -2250 -1396 104 D8 -2130 -1396 105 DMY56 -2010 -1396 106 D9 -1890 -1396 107 DMY57 -1770 -1396 108 D10 -1650 -1396 109 DMY58 -1530 -1396 110 D11 -1410 -1396 111 DMY59 -1290 -1396 112 D12 -1170 -1396 113 DMY60 -1050 -1396 114 D13 -930 -1396 115 DMY61 -810 -1396 116 D14 -690 -1396 117 DMY62 -570 -1396 118 D15 -450 -1396 119 DMY63 -330 -1396 120 VSS(L) -270 -1396 121 VSS(C) -210 -1396 122 VSS(R) -150 -1396 123 DMY64 30 -1396 124 CL 150 -1396 125 DMY65 270 -1396 126 DMY66 330 -1396 127 FLM 450 -1396 128 DMY67 570 -1396 129 DMY68 630 -1396 130 FR 750 -1396 131 DMY69 870 -1396 132 DMY70 930 -1396 133 CLK 1050 -1396 134 DMY71 1170 -1396 135 DMY72 1230 -1396 136 DMY73 1290 -1396 137 OSC1 1350 -1396 138 DMY74 1410 -1396 139 DMY75 1470 -1396 140 OSC2 1650 -1396 141 DMY76 1830 -1396 142 DMY77 1890 -1396 143 VSSH(L) 1950 -1396 144 VSSH(C) 2010 -1396 145 VSSH(R) 2070 -1396 146 DMY78 2250 -1396 147 DMY79 2310 -1396 148 VLCD(L) 2370 -1396 149 VLCD(C) 2430 -1396 150 VLCD(R) 2490 -1396 151 V1(L) 2670 -1396 152 V1(C) 2730 -1396 153 V1(R) 2790 -1396
-4-
HM17CM4096
s PAD coordinates 2
PAD No. 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 Pin name DMY80 V2(L) V2(C) V2(R) V3(L) V3(C) V3(R) DMY81 V4(L) V4(C) V4(R) VREG(L) VREG(C) VREG(R) DMY82 DMY83 VREF(L) VREF(C) VREF(R) DMY84 VBA(L) VBA(C) VBA(R) DMY85 DMY86 DMY87 VEE(L) VEE(C) VEE(R) DMY88 DMY89 VSSH(L) VSSH(C) VSSH(R) DMY90 DMY91 C1+(L) C1+(C) C1+(R) DMY92 C1-(L) C1-(C) C1-(R) DMY93 C2+(L) C2+(C) C2+(R) DMY94 C2-(L) C2-(C) C2-(R) X(m) 2850 2910 2970 3030 3210 3270 3330 3390 3450 3510 3570 3750 3810 3870 3930 3990 4050 4110 4170 4230 4290 4350 4410 4470 4530 4590 4650 4710 4770 4950 5010 5190 5250 5310 5370 5430 5490 5550 5610 5670 5730 5790 5850 5910 5970 6030 6090 6150 6210 6270 6330 Y(m) -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 PAD No. 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 Pin name DMY95 C3+(L) C3+(C) C3+(R) DMY96 C3-(L) C3-(C) C3-(R) DMY97 C4+(L) C4+(C) C4+(R) DMY98 C4-(L) C4-(C) C4-(R) DMY99 C5+(L) C5+(C) C5+(R) DMY100 C5-(L) C5-(C) C5-(R) DMY101 C6+(L) C6+(C) C6+(R) DMY102 C6-(L) C6-(C) C6-(R) DMY103 DMY104 DMY105 DMY106 DMY107 VOUT(L) VOUT(C) VOUT(R) DMY108 COM80 COM79 COM78 COM77 COM76 COM75 COM74 COM73 COM72 COM71 X (m) Y (m) 6390 6450 6510 6570 6630 6690 6750 6810 6870 6930 6990 7050 7110 7170 7230 7290 7350 7410 7470 7530 7590 7650 7710 7770 7830 7890 7950 8010 8070 8130 8190 8250 8310 8370 8430 8490 8550 8610 8670 8730 8910 9023 9068 9113 9158 9203 9248 9293 9338 9383 9428 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396 -1396
(c) (c)
chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) No. 256 COM70 9473 -1396 257 COM69 9518 -1396 258 DMY109 9581 -1396 259 DMY110 9831 -1143 260 COM68 9831 -1080 261 COM67 9831 -1035 262 COM66 9831 -990 263 COM65 9831 -945 264 COM64 9831 -900 265 COM63 9831 -855 266 COM62 9831 -810 267 COM61 9831 -765 268 COM60 9831 -720 269 COM59 9831 -675 270 COM58 9831 -630 271 COM57 9831 -585 272 COM56 9831 -540 273 COM55 9831 -495 274 COM54 9831 -450 275 COM53 9831 -405 276 COM52 9831 -360 277 COM51 9831 -315 278 COM50 9831 -270 279 COM49 9831 -225 280 COM48 9831 -180 281 COM47 9831 -135 282 COM46 9831 -90 283 COM45 9831 -45 284 COM44 9831 0 285 COM43 9831 45 286 COM42 9831 90 287 COM41 9831 135 288 COM40 9831 180 289 COM39 9831 225 290 COM38 9831 270 291 COM37 9831 315 292 COM36 9831 360 293 COM35 9831 405 294 COM34 9831 450 295 COM33 9831 495 296 COM32 9831 540 297 COM31 9831 585 298 COM30 9831 630 299 COM29 9831 675 300 COM28 9831 720 301 COM27 9831 765 302 COM26 9831 810 303 COM25 9831 855 304 COM24 9831 900 305 COM23 9831 945 306 COM22 9831 990
-5-
HM17CM4096
PAD coordinates 3
PAD No. 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 Pin name COM21 COM20 DMY111 DMY112 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6 SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 X(m) 9831 9831 9831 9581 9518 9473 9428 9383 9338 9293 9248 9203 9158 9113 9068 9023 8978 8933 8888 8843 8798 8753 8708 8663 8618 8573 8528 8483 8438 8393 8348 8303 8258 8213 8168 8123 8078 8033 7988 7943 7898 7853 7808 7763 7718 7673 7628 7583 7538 7493 7448 Y(m) PAD No. 1035 358 1080 359 1144 360 1396 361 1396 362 1396 363 1396 364 1396 365 1396 366 1396 367 1396 368 1396 369 1396 370 1396 371 1396 372 1396 373 1396 374 1396 375 1396 376 1396 377 1396 378 1396 379 1396 380 1396 381 1396 382 1396 383 1396 384 1396 385 1396 386 1396 387 1396 388 1396 389 1396 390 1396 391 1396 392 1396 393 1396 394 1396 395 1396 396 1396 397 1396 398 1396 399 1396 400 1396 401 1396 402 1396 403 1396 404 1396 405 1396 406 1396 407 1396 408 Pin name SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23 SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 X (m) Y (m) 7403 7358 7313 7268 7223 7178 7133 7088 7043 6998 6953 6908 6863 6818 6773 6728 6683 6638 6593 6548 6503 6458 6413 6368 6323 6278 6233 6188 6143 6098 6053 6008 5963 5918 5873 5828 5783 5738 5693 5648 5603 5558 5513 5468 5423 5378 5333 5288 5243 5198 5153 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396

chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) No. 409 SEGA26 5108 1396 410 SEGB26 5063 1396 411 SEGC26 5018 1396 412 SEGA27 4973 1396 413 SEGB27 4928 1396 414 SEGC27 4883 1396 415 SEGA28 4838 1396 416 SEGB28 4793 1396 417 SEGC28 4748 1396 418 SEGA29 4703 1396 419 SEGB29 4658 1396 420 SEGC29 4613 1396 421 SEGA30 4568 1396 422 SEGB30 4523 1396 423 SEGC30 4478 1396 424 SEGA31 4433 1396 425 SEGB31 4388 1396 426 SEGC31 4343 1396 427 SEGA32 4298 1396 428 SEGB32 4253 1396 429 SEGC32 4208 1396 430 SEGA33 4163 1396 431 SEGB33 4118 1396 432 SEGC33 4073 1396 433 SEGA34 4028 1396 434 SEGB34 3983 1396 435 SEGC34 3938 1396 436 SEGA35 3893 1396 437 SEGB35 3848 1396 438 SEGC35 3803 1396 439 SEGA36 3758 1396 440 SEGB36 3713 1396 441 SEGC36 3668 1396 442 SEGA37 3623 1396 443 SEGB37 3578 1396 444 SEGC37 3533 1396 445 SEGA38 3488 1396 446 SEGB38 3443 1396 447 SEGC38 3398 1396 448 SEGA39 3353 1396 449 SEGB39 3308 1396 450 SEGC39 3263 1396 451 SEGA40 3218 1396 452 SEGB40 3173 1396 453 SEGC40 3128 1396 454 SEGA41 3083 1396 455 SEGB41 3038 1396 456 SEGC41 2993 1396 457 SEGA42 2948 1396 458 SEGB42 2903 1396 459 SEGC42 2858 1396
-6-
HM17CM4096
s PAD coordinates 4
PAD No. 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 Pin name SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56 SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGC59 X(m) 2813 2768 2723 2678 2633 2588 2543 2498 2453 2408 2363 2318 2273 2228 2183 2138 2093 2048 2003 1958 1913 1868 1823 1778 1733 1688 1643 1598 1553 1508 1463 1418 1373 1328 1283 1238 1193 1148 1103 1058 1013 968 923 878 833 788 743 698 653 608 563 Y(m) 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 PAD No. 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 Pin name SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73 SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 X (m) Y (m) 518 473 428 383 338 293 248 203 158 113 68 23 -23 -68 -113 -158 -203 -248 -293 -338 -383 -428 -473 -518 -563 -608 -653 -698 -743 -788 -833 -878 -923 -968 -1013 -1058 -1103 -1148 -1193 -1238 -1283 -1328 -1373 -1418 -1463 -1508 -1553 -1598 -1643 -1688 -1733 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396

chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) No. 562 SEGA77 -1778 1396 563 SEGB77 -1823 1396 564 SEGC77 -1868 1396 565 SEGA78 -1913 1396 566 SEGB78 -1958 1396 567 SEGC78 -2003 1396 568 SEGA79 -2048 1396 569 SEGB79 -2093 1396 570 SEGC79 -2138 1396 571 SEGA80 -2183 1396 572 SEGB80 -2228 1396 573 SEGC80 -2273 1396 574 SEGA81 -2318 1396 575 SEGB81 -2363 1396 576 SEGC81 -2408 1396 577 SEGA82 -2453 1396 578 SEGB82 -2498 1396 579 SEGC82 -2543 1396 580 SEGA83 -2588 1396 581 SEGB83 -2633 1396 582 SEGC83 -2678 1396 583 SEGA84 -2723 1396 584 SEGB84 -2768 1396 585 SEGC84 -2813 1396 586 SEGA85 -2858 1396 587 SEGB85 -2903 1396 588 SEGC85 -2948 1396 589 SEGA86 -2993 1396 590 SEGB86 -3038 1396 591 SEGC86 -3083 1396 592 SEGA87 -3128 1396 593 SEGB87 -3173 1396 594 SEGC87 -3218 1396 595 SEGA88 -3263 1396 596 SEGB88 -3308 1396 597 SEGC88 -3353 1396 598 SEGA89 -3398 1396 599 SEGB89 -3443 1396 600 SEGC89 -3488 1396 601 SEGA90 -3533 1396 602 SEGB90 -3578 1396 603 SEGC90 -3623 1396 604 SEGA91 -3668 1396 605 SEGB91 -3713 1396 606 SEGC91 -3758 1396 607 SEGA92 -3803 1396 608 SEGB92 -3848 1396 609 SEGC92 -3893 1396 610 SEGA93 -3938 1396 611 SEGB93 -3983 1396 612 SEGC93 -4028 1396
-7-
HM17CM4096
PAD coordinates 5
PAD No. 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 Pin name SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGA96 SEGB96 SEGC96 SEGA97 SEGB97 SEGC97 SEGA98 SEGB98 SEGC98 SEGA99 SEGB99 SEGC99 SEGA100 SEGB100 SEGC100 SEGA101 SEGB101 SEGC101 SEGA102 SEGB102 SEGC102 SEGA103 SEGB103 SEGC103 SEGA104 SEGB104 SEGC104 SEGA105 SEGB105 SEGC105 SEGA106 SEGB106 SEGC106 SEGA107 SEGB107 SEGC107 SEGA108 SEGB108 SEGC108 SEGA109 SEGB109 SEGC109 SEGA110 SEGB110 SEGC110 X(m) -4073 -4118 -4163 -4208 -4253 -4298 -4343 -4388 -4433 -4478 -4523 -4568 -4613 -4658 -4703 -4748 -4793 -4838 -4883 -4928 -4973 -5018 -5063 -5108 -5153 -5198 -5243 -5288 -5333 -5378 -5423 -5468 -5513 -5558 -5603 -5648 -5693 -5738 -5783 -5828 -5873 -5918 -5963 -6008 -6053 -6098 -6143 -6188 -6233 -6278 -6323 Y(m) 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 PAD No. 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 Pin name SEGA111 SEGB111 SEGC111 SEGA112 SEGB112 SEGC112 SEGA113 SEGB113 SEGC113 SEGA114 SEGB114 SEGC114 SEGA115 SEGB115 SEGC115 SEGA116 SEGB116 SEGC116 SEGA117 SEGB117 SEGC117 SEGA118 SEGB118 SEGC118 SEGA119 SEGB119 SEGC119 SEGA120 SEGB120 SEGC120 SEGA121 SEGB121 SEGC121 SEGA122 SEGB122 SEGC122 SEGA123 SEGB123 SEGC123 SEGA124 SEGB124 SEGC124 SEGA125 SEGB125 SEGC125 SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127 X (m) Y (m) -6368 -6413 -6458 -6503 -6548 -6593 -6638 -6683 -6728 -6773 -6818 -6863 -6908 -6953 -6998 -7043 -7088 -7133 -7178 -7223 -7268 -7313 -7358 -7403 -7448 -7493 -7538 -7583 -7628 -7673 -7718 -7763 -7808 -7853 -7898 -7943 -7988 -8033 -8078 -8123 -8168 -8213 -8258 -8303 -8348 -8393 -8438 -8483 -8528 -8573 -8618 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396 1396

chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) No. 715 COM81 -8663 1396 716 COM82 -8708 1396 717 COM83 -8753 1396 718 COM84 -8798 1396 719 COM85 -8843 1396 720 COM86 -8888 1396 721 COM87 -8933 1396 722 COM88 -8978 1396 723 COM89 -9023 1396 724 COM90 -9068 1396 725 COM91 -9113 1396 726 COM92 -9158 1396 727 COM93 -9203 1396 728 COM94 -9248 1396 729 COM95 -9293 1396 730 COM96 -9338 1396 731 COM97 -9383 1396 732 COM98 -9428 1396 733 COM99 -9473 1396 734 COM100 -9518 1396 735 DMY113 -9581 1396 736 DMY114 -9831 1143 737 COM101 -9831 1080 738 COM102 -9831 1035 739 COM103 -9831 990 740 COM104 -9831 945 741 COM105 -9831 900 742 COM106 -9831 855 743 COM107 -9831 810 744 COM108 -9831 765 745 COM109 -9831 720 746 COM110 -9831 675 747 COM111 -9831 630 748 COM112 -9831 585 749 COM113 -9831 540 750 COM114 -9831 495 751 COM115 -9831 450 752 COM116 -9831 405 753 COM117 -9831 360 754 COM118 -9831 315 755 COM119 -9831 270 756 COM120 -9831 225 757 COM121 -9831 180 758 COM122 -9831 135 759 COM123 -9831 90 760 COM124 -9831 45 761 COM125 -9831 0 762 COM126 -9831 -45 763 COM127 -9831 -90 764 COM128 -9831 -135 765 COM129 -9831 -180
-8-
HM17CM4096
PAD coordinates 6
PAD No. 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 Pin name COM130 COM131 COM132 COM133 COM134 COM135 COM136 COM137 COM138 COM139 COM140 COM141 COM142 COM143 COM144 COM145 COM146 COM147 COM148 COM149 DMY115 X(m) -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 -9831 Y(m) -225 -270 -315 -360 -405 -450 -495 -540 -585 -630 -675 -720 -765 -810 -855 -900 -945 -990 -1035 -1080 -1144 PAD No. Pin name

chip size 19840m
2390m ( chip center : 0m 0m ) PAD Pin name X (m) Y (m) X (m) Y (m) No.
-9-
HM17CM4096
BLOCK DIAGRAM
SEGA126 SEGB126 SEGC126 SEGA127 SEGB127 SEGC127
SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1
VDDA VSSH VSS VDD VLCD, V1 ~V4 C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VOUT VEE VREF VBA VREG
%
SEG DRIVER
5 GRADATION CIRCUIT DATA LATCH
COM0 COM1
VSSA
COM DRIVER
SHIFT REGISTER
D14
2 6 1 5 ' 0 ) 4 ( ' 4 ' &
D13 D12 D11 D10 IO BUFFER D9 D8 D7 D6 D5
X
ADDRESS REGISTER CLK OSC2
8 9 3 1 0 0 ' d ( 9
D2/EXCS D1/SDA D0/SCL
INTERNAL BUS
CS
RS
RD
WR
P/S
SEL68
RES
TEST
"
%
8
7
&
9
d
7
&

"
%
D3/SMODE
$
!
"
"
!
f
e
!
"
5
9
'
3
d
8
3
(
5
'
"
!

!
D4/SPOL
8
9
3
1
8
7
5
7
6
X ADDRESS COUNTER
3
RAM INTERFACE
"
!
%
!
!
"
$
#
D15
COM160 COM161
P A Q I @ Q I G H G @AB C H C A Q G CH
@AB
CD
EF
B
G
CH
@AB
CI
P
P
H
CQ
Q
P
D
C
E
P
CH
y
b
x
X
w
a
u
v
h
X
u
g
v
f
X
u
t
S
e
r
Y
d
p
d
X
s
c
W
i
V
r
U
q
T
p
S
i
R
I
P
P
H
CQ
Q
P
D
C
E
P
CH
I
P
P
H
CQ
Q
D
EF
B
G
CH
I
P
P
H
CQ
Q
H
C
A
Q
G
CH
8
!
"
! "
!

FR FLM CL
OSC1
- 10 -
q
"
!
r
q
!
"
!
q
$

%
r
"
%
!
!
n
o
o
n
o m
o
!
q
$

n
n
!
%
!
"
!
p
!
"
o
o
s POWER CIRCUIT BLOCK DIAGRAM
VBA
"
$
"
!
!
q
VREG
n
VREF
E.V.R.
n
"
%
r
$
q
n
C1+ C1C2+ C2C3+ C3C4+ C4C5+ C5C6+ C6VEE
q
r
!
!
t

VOUT
HM17CM4096
V4
V3
V2
V1
VLCD
- 11 l k j i h h g " ! r q ! " r ! s ! r " ! %
HM17CM4096
s PIN DESCRIPTION 1
NAME VDD VSS VSSH VDDA I/O supply supply supply supply FUNCTION Power pin for logic GND pin for logic High voltage GND pin This pin is internally connected to VDD pin. This pin is used when the voltage of each input pin is fixed to VDD level. caution) Do not use to main power pin. This pin is internally connected to VSS pin. This pin is used when the voltage of each input pin is fixed to VSS level. caution) Do not use to main power pin. LCD driver supply voltage * LCD driver power supply port when external power supply is used. When external power is used, voltages should have following relations. VSSVSSA
supply
VLCD V1 V2 V3 V4
supply/O
C1 + C1 C2 + C2 C3 + C3 C4 + C4 C5 + C5 C6 + C6 VBA VREF VEE VOUT VREG RES D0/SCL D1/SDA D2/EXCS D3/SMODE D4/SPOL
O O O O O O O I supply supply/O O I I/O I/O I/O I/O I/O
D5,D6,D7
I/O
- 12 -
HM17CM4096
s PIN DESCRIPTION 2
NAME D8,D9,D10,D11, D12,D13,D14,D15 CS RS I/O I/O FUNCTION Connect to data bus to MPU with 8bit bi-directional bus. Used as MSB 8bit data bus in the 16bit data RAM transfer mode Set to "L" or "H" when not used. Chip selection pin. Data in-out is possible when CS = "L". Input data selection pin. Distinguish bus data from CPU whether instruction or display data. RS class RD (E) I H instruction L display data
I I
WR (R/W)
I
<80 series CPU interface (P/S="H",SEL68="L")> RD signal connection port of 80 series CPU. Data bus goes to output state at RD = "L". <68 series CPU interface (P/S="H",SEL68="H")> Enable signal connection port of 68 series CPU. Active status when this signal is at "H". <80 series CPU interface (P/S="H",SEL68="L")> WR signal connection port of 80 series CPU. Active at "L" and data bus signal is taken at the rising edge of WR. <68 series CPU interface (P/S="H",SEL68="H")> Read write control signal , R/W connection port of 68-series MPU. H L R/W status read write
SEL68
I
CPU interface selection port SEL68 H status 68 series
P/S chip select data/ command data
L 80 series
read/ write serial clock
P/S
I
Serial / parallel interface selection port
H L
u
CS CS
RS RS
D0~D7 SDA(D1)
RD, WR
write only
SCL (D0)
TEST CL
I I/O
P/S = "L" :serial interface selection ,D15~D5 goes to Hi-Z state. Fix RD, WR to "H" or "L". Test port. Fix to "L". Latching signal pin of display data. Display line counter is counted up at the rising edge and LCD driving signal is generated at the falling edge LCD synchronous signal (first line marker) I/O pin. Display start address is loaded in the display line counter at FLM = "H". Alternated display signal of LCD driver output I/O pin.
FLM
I/O
FR
I/O
- 13 -
HM17CM4096
PIN DESCRIPTION 4
NAME SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127 I/O O FUNCTION Segment drive port Segment output from display RAM data mode Non-lighted lighted Normal 0 1 Reverse 1 0 The output level is selected among VLCD, V2, V3, VSS by the combination of FR signal and RAM data (B/W mode) FR signal display RAM data Normal mode Reverse mode COM0~COM162 O V2 VLCD VLCD V2 V3 VSS VSS V3
Common driver output The output level is selected among VLCD, V1, V4 and VSS by the combination of FR and scan data. data H L H L FR H H L L Output level VSS V1 VLCD V4
OSC1, OSC2
I O
CLK
I/O
External reference clock input pin Open or fix "L" when using internal oscillator clock . In this case, OSC1 goes to VSS level. Connect external oscillating source to OSC1 port or connect resistor between OSC1 and OSC2 when using external oscillator. Input / output pin for display timing clock External clock is applied to chip through CLK pin when internal clock is not used.
- 14 -
HM17CM4096
s FUNCTION DESCRIPTION (1) CPU interface (1-1) Selection of interface type HM17CM4096 receives data through 8 bit parallel I/O(D0~D7)v 16 bit parallel I/O(D0~D15) or divided into serial data input (SDA, SCL). Parallel or serial selection is decided by P/S pin setting. Parallel or serial selection is possible as following table. Reading out from internal register or RAM is not possible at serial interface mode.
TABLE P/S H L Type Parallel input Serial input CS CS RS RS RD RD WR WR SEL68 SEL68 SDA SCL SDA SCL data D0~D7 (D0~D15) -
RS CS caution 1) "-" mark item : Fix to "H" or "L"
(1-2) Parallel input In the parallel interface mode selected by P/S port, parallel data is transferred from the 8bit/16bit MPU through data bus. SEL68 port setting makes 80-series or 68-series interface selection
TABLE SEL68 H L CPU type 68 series CPU 80 series CPU CS CS CS RS RS RS RD E RD WR R/W WR data D0~D7 (D0~D15) D0~D7 (D0~D15)
(1-3) Data identification Combinations of RS, RD, and WR signals identify contents of 8bit data bus.
TABLE 68 series RS 1 1 0 0 R/W 1 0 1 0 80 series FUNCTION RD 0 1 0 1 WR 1 0 1 0 Read out from internal register Write in to internal register Read display data Write display data
(1-4) Serial interface 2 types of serial interface (3 line type mode, 4 line type mode) are available by selecting SMODE pin.
TABEL SMODE H L
Serial interface mode 3 line type 4 line type
- 15 -
HM17CM4096
(1-5) 4 line type serial interface 4 line serial interface by SDA and SCL is possible at chip selection state (CS="L") When chip is not selected, internal shift register and counter are reset to initial value. Serial input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence of D7, , D1, D0 and converted into 8-bit parallel data at the rising edge of 8th serial clock. Serial data (SDA) are identified to display data or command by RS input.
TABLE RS H L
w
Data contents command Display data
Make serial clock (SCL) "L" at the non-access period and after 8bit data transfer. SDA and SCL signals are sensitive to external noise. To prevent mal-function, chip selector state should be released (CS = "H") after 8bit data transfer as shown in the following figure.
CS RS SDA SCL 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 VALID D0
4 line serial interface
(1-6) 3 line type serial interface 3-line serial interface by SDA and SCL is possible at chip selection state (CS="L") When chip is not selected, internal shift register and counter are reset to initial value. Input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence of RS, D7 , ,D1, D0, and converted to 8bit parallel data and handled at the rising edge of 9th serial clock. Serial data (SDA) are identified to display data or command by RS bit data at the rising of first serial clock (SCL) and state of command data bit polarity shift pin (SPOL).
TABLE RS L H SPOL=L Data identify Display data command RS L H SPOL=H Data identify command Display data
x
- 16 -
HM17CM4096
Serial clock (SCL) should go to "L" at the non-access period and after 9bit data transfer. SDA and SCL signals are sensitive to external noise. To prevent miss operation chip selector state should be released (CS = "H") after 9bit data transfer as shown in the following figure.
CS SDA SCL 1 2 3 4 5 6 7 8 9 RS D7 D6 D5 D4 D3 D2 D1 D0
3line serial interface
(1-7) One systematization of CS under some interface In some operation mode, data interface control is possible. Data in-out is possible under the condition, CS = "L".
(2) DDRAM and internal register access DDRAM and internal register are accessed by data bus D0~D7(D0~D15), chip select pin (CS), DDRAM / register select pin (RS), read / write control pin (RD) or WR pin. When CS="H", it is in non-selective state and DDRAM and internal register access is impossible. During access, Set CS="L". Access selection to DDRAM or internal register is controlled by RS input.
TABLE RS L H Data contents Display RAM data Internal command register
Write process starts after address setting and then the data on the 8bit data bus D0~D7 or 16bit data bus D0~D15 will be written in by CPU. The data is written at the rising edge of WR (80 series) or falling edge of E (68 series). Internally, bus holder data is processed to data bus and data are written to bus holder from CPU until next cycle. After address setting, data of assigned address are read at the 1st and 3rd clock, which means it needs dummy read at the 2nd clock. There are rules at reading data out of display RAM, after address setting, the data of assigned address is shown directly after the end of the read command, so pay attention that assigned data is available at 2nd timing step. In other words, 1 cycle dummy read is needed after address setting and write cycle.
- 17 -
HM17CM4096
DATA WRITE IN OPERATION D0~D15 WR
yz{
n
n+1
n+2
n+3
n+4
BUS HOLDER
|} z~
n
n+1
n+2
n+3
n+4
WR
DATA READ OUT OPERATION WR D0~D7(D0~D15) n address set n RD caution) When 16 bit mode, do write in and read out by 16 bit not only RAM access but also command setting. dummy read n data read n address n+1 data read n+1 address n+2 data read n+2 address
(3) Read out of internal register Read out is possible not only from DDRAM, but also from the internal register. read (0~FH) are allocated in each register. Read out is executed after writing read-out register address to internal register.
WR D0~D7 M Address set for register read RD Internal register read out sequence RE register set:100 Internal register read address set set RE of register to be read out Internal register read m Internal register read N Address set for register read n Internal register read
Addresses for
When register is read out, upper 4 bit data are "1111". Non-used bits of active registers are "0". When non-used registers are read out, upper 4 bits are "1111" and lower 4 bits are "0000".
- 18 -
HM17CM4096
(4) 16 bit data access to DDRAM It is possible to write in DDRAM by 16-bits access with the data of 16 bits data bus D0~D15. 16 bits data access mode is possible by setting the value of WLS register to "1".
TABEL WLS L H Access mode 8 bit 16 bit
Each command should be set to 8-bits(D0~D7) as well as to 16-bit access mode. 16-bit access is available at display RAM access. (5) Display start line register When displaying the DDRAM data, it is the contents of Y address register that is corresponding to display start line. The data of Y address is displayed on the display start line depending on the value of the shift command register and the display start line register. The data of this register are preset to the display line counter per FLM signal transition. Line counter is counted up in synchronization with CL input and generates line address that read out 384bit data from DDRAM to LCD driver circuit. (6) DDRAM addressing This IC includes display memory Bit mapped that is composed of 1,536 bit of X direction (12bitx128) and 162bit of Y direction. In gray mode, neighboring 4-bit data are displayed by segment driver with 16 grays, respectively. 3 outputs of segment driver compose 1 pixel of RGB and 128x162 pixels are displayed with 4096 color (16grayx16grayx16gray). Address area of X direction is varied according to accessed data length. The area of X direction is 0H~FFH at 8bit access mode and 0H~7FH at 16bit access mode.
*
8BIT access X-address 0H 0H 8bit 1H 8bit FEH 8bit FFH 8bit
Y-address
51H
*
8bit
8bit
8bit
8bit
16 BIT access X-address 0H 0H 16bit 7FH 16bit
Y-address
51H
16bit
16bit
- 19 -
HM17CM4096
In the Black & white mode, the MSBs of 4 bit corresponding with RGB are used to display data. And so, 128x162 dot gray display or 384 162 B/W mode display is possible. Display RAM is accessed with X address and Y address from CPU by 8 bit or 16 bit unit. X address and Y address can be increased automatically by setting status of control register. The address is increased per every read and write of display RAM by CPU. ( Please see detail description at command function.) X direction is selected by X address and Y direction is selected by Y address. Please do not set the address on non-effective area and it is forbidden to set address on outside area in each case. 384bit display data of Y direction are read out to display latch at rising edge of CL signal per 1 line cycle and this data comes out from display latch at falling edge of CL signal. Display start line address register is preset to line counter at "H" state of FLM signal which changes per one frame cycle and the address is counted up with synchronized CL input. Display line address counter is synchronized by timing signals of LCD driver, and it operates independently with X, Y address counters.
(7) Window address assign of display RAM This IC can be accessed to display RAM by window area designation in addition to access to display RAM designated by X and Y address. Through address space of all display address, specific area of RAM can be accessed by designated two points. The start point of two point addresses is assigned by normal X address and Y address register and the end point of them is done by X end address and Y end address register value. Designated inner addresses depend on WLS bit. Read modified write action can be taken by AIM="1". In case of using window area accessing mode, you must set start point X address, Y address in sequence and end point X address, Y address in sequence after executing Win command (WIN="1", auto increase mode AXI="1", AYI="1") and then access to Display RAM. And set start point and end point not to be designated to access the outside of available address area. Address set value should be taken to set AX EX ( end point of X address ) and AYEY ( end point of Y address ).
X direction
(X, Y) address designation
Y direction
Window display area
end address designation (X, Y) All display RAM area
- 20 -
HM17CM4096
(8) display RAM data and LCD Display RAM data related with one dot of LCD is dependent on REV register. Normal display and reverse display by REV register are set up as follows.
TABLE REV L H
Display normal reverse
RAM data 0 1 0 1
(9) Segment display output order/reverse set up The order of display outputs, SEGA0, SEGB0, SEGC0 to SEGA127, SEGB127, and can be reversed by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing IC when assembling an LCD panel module.
- 21 -
8 bit 0X10 0101 0100 0001 0000 11X1 11X0 10X1 10X0
16 bit
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 X=00H Palette A X=FEH X=00H X=FEH X=00H X=00H X=00H
(10) Relation between RAM X-address and Bit Assign
RAM X-Address / Bit Assign TABLE 1 ( 4096 color mode )
D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 X=01H X=02H X=FCH X=02H X=FCH X=01H X=7EH X=7EH X=FDH X=02H X=03H X=03H X=FDH X=FCH X=02H
0X11
X=BEH(L)
SEG0
Palette B
X=7FH
X=7FH
X=01H
X=FFH
X=BFH X=01H X=FFH X=01H D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X=FCH X=02H X=BDH X=7EH X=7EH X=01H X=01H X=FDH X=03H X=FDH X=03H X=BEH X=FEH X=00H X=FEH X=00H X=7FH X=7FH X=00H X=00H X=FFH X=01H X=BFH X=FFH X=01H
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Palette C
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2
Palette A
X=BDH
SEG1
Palette C
Palette B
X=BEH(H)
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 Palette A
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
MODE WLS ABS HSW REF R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
X=01H(L)
SEG126
Palette B
X=02H
Palette C Palette A
X=00H
SEG127
Palette B Palette C
X=01H(H)
HM17CM4096
- 22 -
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1 D7 D6 D5 D4 D2 D1 D0 D7 D4 D3 D2 D1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1 D15 D14 D13 D12 D10 D9 D8 D7 D4 D3 D2 D1
R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
HM17CM4096
RAM X-Address / Bit Assign TABLE 2 ( 256 color mode )
SEG0 Palette R Palette G Palette B Palette R SEG1 Palette G Palette B Palette R SEG126 Palette G Palette B Palette R SEG127 Palette G Palette B
Mode WLS ABS HSW REF C256 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
assignment
X=00H
X=01H
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
8 bit
X=7FH
X=7EH
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Remark 1) Under 256 color mode, the lowest vacant bits are filled with "1". 2) There are no relations between the wrote-in data when C256="0" and C256="1".
SWAP OPERATION TABLE
SWAP Palette A G3 R3 R2 R1 R0 Palette B G2 G1 G0 B3 Palette C B2 B1 B0 REF
0 1 0 1
0 1 1 0
SEGAx SEGCx
SEGBx SEGBx
SEGCx SEGAx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
0XX11
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X=01H X=00H
0XX01
R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 X=7EH X=7FH
- 23 -
xq
t w
r w
q
f
t
eg
ef
es
er
eq
ep
ei
eh
eg
ef
es
er
eq
ep
ei
eh
eg
ef
d d
b b
a a

V V
Y Y
X X
W W
a a
b b
a a

V V
Y Y
X X
W W
U U
V V
U U
T T
c c
b b
a a

V V
Y Y
X X
W W
U U
V V
U U
T T
U U
V V
U U
T T
96 B5 B4 B3
95
94
93
C6
C5
C4
C3 B6 B5 B4 B3
96
95
94
93
5 5 @ @ 5 @ 5 @ @
5 @
5 @
5 @
5 @
5 @
5 @
5 5 @ @ 5 @ 5 @ 5 @
5 @
5 @
5 @
5
4 4 4 4
4
4
4 A
A
A
A
4
4
4
4 4 4 4 4
4
4
4
4 A
A
) ) ) )
)
)
)
0
0
0
0 0 0 0 0
0
0
0
0
(1
(0
()
(6
(5
(4
(3
(2
(1
(0
()
(6
(5
(4
(3
(2
(1
(0
()
(6
(5
(4
(3
(2
(1
' '
& &
% %
P P
F F
I I
H H
G G
& &
& &
% %
P P
F F
I I
H H
G G
E E
F F
E E
D D
S S
& &
% %
P P
F F
I I
H H
G G
E E
F F
E E
D D
R R
& &
Q Q
P P
F F
I I
H H
G G
E E
F F
E E
D D
E E
F F
E E
D D
96 B6 B5 B4 B3
95
94
93
C6
C5
C4
C3 B6 B5 B4 B3
96
95
5 7 @ @
5 @
5 @
5 @
5 @
5 @
5 @
5 @
5 @
5 @
5 @
5 5 @
5 @ @
5 @
5 @
5 @
5 @
A 4
4
4
4
A
4
4
4
4
A
4
4
4
4
A
A 4
4
4
4
A
4
4
) ) ) ) )
)
)
)
0
0
0
0 0 0 0 0
0
0
7
(0
()
(6
(5
(4
(3
(2
(1
(0
()
(6
(5
(4
(3
(2
(1
(0
()
(6
(5
(4
(3
(2
(1
' '
& &
% %

! !
! !
# #

$ $
! !
# #

" "
! !

a a
a
a
e
e
c
ca
ca
ca e
e
e
e
c
ca
ca
ca
a a a a a
a
a
a a
a
a
aa
a
aa
a
aa a a a a a a a
a
a
a
a
e
ae
ae
ae
ae
ae
ae
a
a
a
a a
a
a
a a a a a
a
a
a
a
a
a
ae ae ae
ae
ae
ae ae
ae
ae
ae ae ae ae ae
ae
ae
ae
ae a
/
/
/
/
/
/
/
/
/
/
/
/
/u
/u
/
/
/
/
/
/
/
/
/u
/u
a
a
a
e e e u o e e u o e e u o e e
a
a
a
a
au
ao
a
a
a
a
a
a
a
a
a
a
a
a
a
o o o o o o o o i i n n i i i i i i i i i i
o o o o o o o o i i n n i i i i i i i i i i o o o o i i n n i i i i i i i i i i o o o o i i n n i i i i i i i i i i
a a
a a
a
e
e
e
e
c
ca
ca
ca e
e
e
e
c
ca
a
a
a a
a a
a
a
a
a
a
a
a a
aa a
aa a
aa a a a a a a a a
a
a
e
ae
ae
ae
ae
ae
ae
a a a a a
a
a
a
a
a
a
a a a a a
a
a
ae ae ae ae ae
ae
ae
ae
ae
ae
ae
ae ae ae ae ae
ae
ae
AE
AE
AE
AE
AE
AE
AE
AE
AE
AE
I
AA
AI
AI
AE
AE
AE
AE
AC
AAE
AA
AA
AI
AI
AE
E
E
E
C
AE
A
E
E
E
C

| |
(c) (c)

| |

*
RAM DATA WRITE - IN TABLE
.........
(0
()
94
93
5 @
5
4
4
0
0
(0
()
ae
ae
/
/
au
ao
ca
ca
a
a
a
ae
ae
AE
AE
AE
A
.
.
.
.
HM17CM4096
- 24 vs xp vr vq vp ys yr yq yp xs xr xq xp vs vr vq vp ys yr yq yp xs xr xq xp vs vr vq vp ys yr yq yp xs xr xq xp vs vr vq vp r w r w r w r w w r r w r w r w w r r w r w r w r w r w r w r w r q q q q q q q q q q q q q w q q q q r w r w r w w r r w r w r w r w r w r w r w w r s w s w s w w s s w s w s w s w s w s w s w s f f f f f g g g g g g g g g g g g u a a u c c es er eq ep ei eh eg ef es er eq ep ei eh eg ef es er eq ep ei eh eg ef R R P P F F I I H H G G E E F F E E D D % % P P F F I I H H G G E E F F E E D D Q Q P P F F I I H H G G E E F F E E D D C6 C5 C4 C3 96 B6 B5 B4 B3 95 94 93 C6 C5 C4 C3 96 B6 B5 B4 B3 95 94 93 A A @ 5 @ 5 @ 5 @ @ 5 5 @ 5 @ 5 @ 5 @ 5 @ 5 @ 5 @ 5 A A A A @ 6 @ 6 @ 6 @ @ 6 6 @ 6 @ 6 @ 6 @ 6 @ 6 @ 6 @ 6 A A A A 8 8 Q Q 8 8 (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () S S P P F F I I H H G G E E F F E E D D R R P P F F I I H H G G E E F F E E D D % % P P F F I I H H G G E E F F E E D D Q Q P P F F I I H H G G E E F F E E D D C6 C5 C4 C3 B6 B5 B4 B3 96 95 94 93 C6 C5 C4 C3 B6 B5 B4 B3 96 95 94 93 A @ 5 @ 5 @ 5 @ @ 5 A A 5 @ 5 @ 5 @ 5 @ A 5 @ 5 @ 5 @ 5 A @ 6 @ 6 @ 6 @ @ 6 A A 6 @ 6 @ 6 @ 6 @ A 6 @ 6 @ 6 @ 6 8 8 8 8 8 8 (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () (6 (5 (4 (3 (2 (1 (0 () (c) (c) | | | | y y y y y y o o o o o i i n n i i i i i i i i i i o o o i i n n i i i i i i i i i i a a a a a a e e e e c ca ca ca ae ae ae ae a a a a aa a a aa a a aa a a a e a e a e a a a a a a a a a a a e a c a ca a ca a ca ae ae ae ae a a a aa a aa a aa a a a a a a a a a a a a a a a a a a a a a a u u o o o o / / / / / / / / / / / / / / / / / / / / /u /u / / / / / / / / /u /u a a a a a a a a au ao a a a a au ao a a a a a a a a a a a a O O O Ox O OO O OO a a a a O U ae ae ae e e e e ae c ca ca ca ae a a a a U aa U U U U U U U UY U U UU O O O O O a a a aa a aa a aa a a a a a a a a a a a a a a aa a aa a a a a a a a a a a a a a N N I I * * (R) AE AE AE AE AE AE AE AE AE AC AAE AA AA AI AI AE AE AE AE AC AAE AA AA AA A 1/23/4 1/4 E E E C AE A
HM17CM4096
*
WRITE IN / READ IN BITMAP ( 16 BIT MODE )
REF=0, SWAP=0
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
WRITE IN DATA
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=0, SWAP=1
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=1, SWAP=0
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=1, SWAP=1
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
- 25 -
HM17CM4096
*
READ OUT AFTER WROTE IN DATA ( 16 BIT MODE )
REF=0, SWAP=0
D15 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 D0 0 (E4F2H)
WRITE IN DATA
READ IN DATA
D15 1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0 0
(E4F2H)
REF=0, SWAP=1
WRITE IN DATA D15 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 D0 0 (E4F2H)
READ IN DATA
D15 0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
D0 1
(4F27H)
REF=1, SWAP=0
WRITE IN DATA D15 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 D0 0 (E4F2H)
READ IN DATA
D15 1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0 0
(E4F2H)
REF=1, SWAP=1
WRITE IN DATA D15 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 D0 0 (E4F2H)
READ IN DATA
D15 0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
D0 1
(4F27H)
- 26 -
HM17CM4096
*
WRITE IN / READ IN BITMAP ( 8 BIT MODE )
REF=0, SWAP=0
D0 D1 D2 D3 D4 D5 D6 D7
WRITE IN DATA
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
REF=0, SWAP=1
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
REF=1, SWAP=0
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
REF=1, SWAP=1
WRITE IN DATA D0 D1 D2 D3 D4 D5 D6 D7
SEGMENT DATA
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
- 27 -
HM17CM4096
*
READ OUT AFTER WROTE IN DATA ( 8 BIT MODE )
REF=0, SWAP=0
D15 1 1 1 0 0 1 0 D0 0 (E4H)
WRITE IN DATA
READ IN DATA
D15 1
1
1
0
0
1
0
D0 0
(E4H)
REF=0, SWAP=1
WRITE IN DATA D15 1 1 1 0 0 1 0 D0 0 (E4H)
READ IN DATA
D15 0
0
1
0
0
1
1
D0 1
(27H)
REF=1, SWAP=0
WRITE IN DATA D15 1 1 1 0 0 1 0 D0 0 (E4H)
READ IN DATA
D15 1
1
1
0
0
1
0
D0 0
(E4H)
REF=1, SWAP=1
WRITE IN DATA D15 1 1 1 0 0 1 0 D0 0 (E4H)
READ IN DATA
D15 0
0
1
0
0
1
1
D0 1
(27H)
- 28 -
HM17CM4096
(11) display data structure and gradation control For the purpose of gradation control, information per pixel requires multiple bits. This IC has 4 bit per output to achieve the gradation display. This IC is connected to an STN color LCD panel by three segment port units and one pixel consists of three outputs of segment driver, and so 4096 color ( 4 bits x 4 bits x 4 bits ) display on 128 x 162 pixels is realized. Since one pixel data can be processed by one time access to memory, the data can be rewritten fast and naturally. The weight of each data bit is dependent on the status of SWAP register bit and REF register when data is written to the display RAM.
*
ACCESS when (REF, SWAP)=(0, 0) or (1, 1) SEGBi SEGAi
SEGCi
i=0~127
0 LSB
0
0
0 D1
0 D2
0 D3
notice) internal access X address :nH~7FH (access when REF="0") :7FH~nH (access when REF="1")
*
ACCESS when (REF, SWAP)=(0, 1) or (1, 0) SEGBi SEGAi
Palette Cj Aj

1 MSB
1
1
0 D1
0 D2
0 D3
notice) internal access X address :nH~7FH (access when REF="0") :7FH~nH (access when REF="1")
Palette Aj

Aj
Palette Bj
Palette Cj
Gradation palette j=0~15 Gradation control circuit.
0
1
0
1
0
1
1
1
1 MSB
Display RAM data
MSB LSB
MSB LSB
0 D4
1 D7
0 D8
1 D9
0
1
1 D13
1
1
D10 D12
D14 D15
CPU access data X address :nH
SEGCi
i=0~127
Palette Bj
Palette Aj
Gradation palette j=0~15 Gradation control circuit.
1
0
1
0
1
0
0
0
0 LSB
Display RAM data
LSB MSB
LSB MSB
0 D4
1 D7
0 D8
1 D9
0
1
1 D13
1
1
D10 D12
D14 D15
CPU access data X address :nH
- 29 -
HM17CM4096
When display RAM is accessed by 16 bit data width, the weight of each data bit is dependent on the status of SWAP register and REF register, the same method as 8 bit access.
12 bit data are extracted from 16 bit address, and then transmitted to gradation palettes. At 8 bit - 4096 gradation mode , two 8 bit address map is used at display. More detail information, please refer to bit assign table.
*
ACCESS when (REF, SWAP)=(0, 0) or (1, 1) SEGBi SEGAi
SEGCi
i=0~127
0 LSB
0
0
0 D1
0 D2
0 D3
X address :nH
notice) internal access X address :nH~FFH (access when REF="0") :FFH~nH (access when REF="1")
*
ACCESS when (REF, SWAP)=(0, 1) or (1, 0) SEGBi SEGAi
Palette Cj Aj

1 MSB
1
1
0 D1
0 D2
0 D3
X address :nH
notice) internal access X address :nH~FFH (access when REF="0") :FFH~nH (access when REF="1")
Palette Aj

Aj
Palette Bj
Palette Cj
Gradation palette j=0~15 Gradation control circuit.
0
1
0
1
0
1
1
1
1 MSB
Display RAM data
MSB LSB
MSB LSB
0 D4
1 D7
0 D0
1 D1
0 D2
1 D4
1 D5
1 D6
1 D7
CPU access data
X address :n+1H
SEGCi
i=0~127
Palette Bj
Palette Aj
Gradation palette j=0~15 Gradation control circuit.
1
0
1
0
1
0
0
0
0 LSB
Display RAM data
LSB MSB
LSB MSB
0 D4
1 D7
0 D0
1 D1
0 D2
1 D4
1 D5
1 D6
1 D7
CPU access data
X address :n+1H
- 30 -
HM17CM4096
s DUTY RATIO SETTING fFLM Frame Frequency) Dot width Duty setting Variable 16 gradation Fixed 8 gradation in YBW(fosc=25kHz) direction (fosc=763kHz) (fosc=172kHz) 162 160 144 133 128 112 96 80 72 64 56 48 40 32 24 16 1/163Duty 1/160Duty 1/144Duty 1/133Duty 1/128Duty 1/112Duty 1/96Duty 1/80Duty 1/72Duty 1/64Duty 1/56Duty 1/48Duty 1/40Duty 1/32Duty 1/24Duty 1/16Duty fosc/(62*D) fosc/(62*D) fosc/(62*D) fosc/(62*D) fosc/(62*D) fosc/(62*D) fosc/(62*D) fosc/(62*D*2) fosc/(62*D*2) fosc/(62*D*2) fosc/(62*D*2) fosc/(62*D*4) fosc/(62*D*4) fosc/(62*D*4) fosc/(62*D*8) fosc/(62*D*8) fosc/(14*D) fosc/(14*D) fosc/(14*D) fosc/(14*D) fosc/(14*D) fosc/(14*D) fosc/(14*D) fosc/(14*D*2) fosc/(14*D*2) fosc/(14*D*2) fosc/(14*D*2) fosc/(14*D*4) fosc/(14*D*4) fosc/(14*D*4) fosc/(14*D*8) fosc/(14*D*8) fosc/(2*D) fosc/(2*D) fosc/(2*D) fosc/(2*D) fosc/(2*D) fosc/(2*D) fosc/(2*D) fosc/(2*D*2) fosc/(2*D*2) fosc/(2*D*2) fosc/(2*D*2) fosc/(2*D*4) fosc/(2*D*4) fosc/(2*D*4) fosc/(2*D*8) fosc/(2*D*8) DS3 DS2 DS1 DS0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
s COMMON START LINE SET SC3 SC2 SC1 SC0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 SHIFT="0" COM0 COM1 COM9 COM14 COM17 COM25 COM33 COM41 COM49 COM57 COM65 COM73 COM122 COM130 COM138 COM146

SHIFT="1" COM161 COM160 COM152 COM146 COM144 COM136 COM128 COM120 COM112 COM104 COM96 COM88 COM39 COM31 COM23 COM15

- 31 -
HM17CM4096
s BIAS SETTING B2 B1 B0 000 001 010 011 100 101 110 111 Bias setting 1/9Bias 1/8Bias 1/7Bias 1/6Bias 1/5Bias 1/10Bias 1/11Bias 1/12Bias
s GRADATION MODE SETTING
PWM C256 MON
Gradation mode Variable 16 gradation mode (variable 4096 color display) Fixed 8 gradation mode (fixed 256 color display) BW mode (8 color display) 256 color mode
1 pixel RAM data R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0
Palette setting
0 0 1 *
00 1 * * * * 1
EEEEEEEE EEEXEEEX
E E E E E variable

EEXX
X fixed
EXXXEXXXEXXX X fixed D7 D6 D5 "1' D4 D3 D2 "1" D1 D0 "1" "1" E ( variable )
Remark ) X means non-effective data
s 16 BIT RAM ACCESS SETTING (WLS = "1")
ABS Access mode 0 1 Normal access mode 1 Normal access mode 2 D15 D14 D13 D12 D11 D10 R3 X R2 X R1 X R0 X X R3 G3 R2 D9 G2 R1 D8 G1 R0 D7 G0 G3 D6 X G2 D5 X G1 D4 B3 G0 D3 B2 B3
D2 D1 D0 B1 B0 X B2 B1 B0
Remark ) X means non-effective data
s 8 BIT RAM ACCESS SETTING (WLS = "0")
Normal access mode 1 (1 frame data write in during 2 write cycle) Normal access mode 2 (1 frame data write in during 2 write cycle) High speed access mode (2 frame data write in during 3 write cycle) 256 Color Mode
l k j i h g f e d
HSW ABS C256 Access mode 0 0 0 1 0 0 1 2 1 2 1 2 3
R3 G0 X G3 R3 B3 G3 R3
R2 X X G2 R2 B2 G2 R2
R1 X X G1 R1 B1 G1 R1
R0 B3 X G0 R0 B0 G0 G3
X B2 R3 B3 G3 R3 B3 G2
G3 B1 R2 B2 G2 R2 B2 G1
G2 B0 R1 B1 G1 R1 B1 B3
G1 X R0 B0 G0 R0 B0 B2
1 *
* *
0 1
Remark ) X means non-effective data
s GRADATION MODE SETTING (WLS = "1") FDC1 0 0 1 1 FDC2 0 1 0 1 Boosting clock Normal speed 2 normal speed 3 normal speed 4 normal speed
m m m
- 32 -
HM17CM4096
(12) GRADATION PALETTE This IC has two gradation display modes, the fixed gradation display mode and the variable gradation display mode. Select mode by setting the gradation display mode register (PWM command) to the purpose.
PWM="0" : variable gradation mode among 32-level gradations. PWM="1" : fixed 16 gradation mode
To select the best gradation level suited to LCD panel at variable gradation display mode, use the gradation palette register among 32-level gradation palettes. Segment driver outputs are set by selected 8-level gradation palette. The gradation palette register provides three registers ( palette Aj, Bj, and Cj : j=015 ) for the segment driver outputs, SEGAi(0127), SEGBi(0127), and SEGCi(0127) . Each register consists of a 5-bit register, selecting 16 gradations from the 32 gradation pattern. GRADATION PALETTE INITIAL VALUE
(palette Aj, palette Bj, palette Cj ; j = 0 ~ 15 )
RAM data 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Register name Gradation palette 0 Gradation palette 1 Gradation palette 2 Gradation palette 3 Gradation palette 4 Gradation palette 5 Gradation palette 6 Gradation palette 7 Gradation palette 8 Gradation palette 9 Gradation palette 10 Gradation palette 11 Gradation palette 12 Gradation palette 13 Gradation palette 14 Gradation palette 15
Initial value 0/31 3/31 5/31 7/31 9/31 11/31 13/31 15/31 17/31 19/31 21/31 23/31 25/31 27/31 29/31 31/31
GRADATION PALETTE TABLE ( PWM = "1", MON = "0" ; fixed 8 gradation mode )
~ } | z { z y x w v u n (c) (R) | t r s r q (R) (c) p o (R) n
- 33 -
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
i
e
i
c
ae
i
c
ae
e
e
e
e
i
c
ae
i
c
ae
e
e
e
e
i
c
ae
i
c
ae
e
e
e
e
i
c
ae
i
c
ae
e
e
e
e
i
c
ae
i
c
ae
e
e
e
e
i
c
ae
i
c
ae
e
e
e
I
O
I
E
O
I
E
I
I
O
I
E
O
I
E
I
I
O
I
E
O
I
E
I
I
O
I
E
O
I
E
I
A
A
A
A
A
A
GRADATION PALETTE TABLE ( MON = "1" ; BW mode )
GRADATION PALETTE TABLE ( PWM = "0", MON = "0" ; variable 16 gradation mode )
(palette Aj, palette Bj, palette Cj ; j = 0 ~ 15 )
HM17CM4096
- 34 a u u u a i u u u i o i u e e ae ae u u ae e ae o / o o e a e e e e c ae a a a a a a a a a a a a a a i a i a a a a e e a e e e e c ae a a a a a n a i a a a a a a o n i i a a a e a a e e e e c ae a a a a o n a a i a a a a a o n i a i a a e n a e e e e c ae a a a a n a i i a a a a a e n i i i a a e a a e e e e c ae a a a a a n a a a i a a a a n n i a a i a e i a e e e e c ae a a a a a n a i a i a a a a i n i i a i a i e a e e e e c ae a a a a a a a a i i a a a a o a i a i i a i e o e e e e c ae a a a a o a a i i i a a a a o a i i i i a i e o e e e e c ae a a a a a a a a a i a a a e a i a a a i i e o e e e e c ae a a a a a a a i a a i a a a n a i i a a i i e e e e e c ae a a a a a a a a i a i a a a i a i a i a i i e e e e e e c ae a a a a a a a a Y U I I I O I N O I I I I I E E O O O U O O O I I O O O U I O O I I N x I I I I I E E O O O U O I O I I O O O O I I O I I N O I I I I I E E O O O O O O I I I O O O x I O I I I O O O O O I I I I N I I I I I I E E E E C AE AE AE AE AE AE A 3/4 * 1/2 * 1/4 *
HM17CM4096
(13) DISPLAY TIMMING GENERATOR The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for internal operation by inputting the original oscillating clock CK or by the oscillating circuit. (14) SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT. The latch signal from line counter clock to display data latch circuit is generated from display clock (CL). Synchronized with the display clock, the line addresses of Display RAM are generated and 384-bit display data are latched to display-data latching circuit and then output to the LCD drive circuit (SEG output port). Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so MPU can access it with no relationship with the read-out operation of the display data. GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM). The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock (CL). The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal state ( inverse FR signal level per 1 frame ). But by setting up data (n-1) on n-line inversion register and "1" on n-line alternated command (NLIN), n-line inverse waveform can be generated. DISPLAY DATA LATCH CIRCUIT This circuit latches the display data from display RAM to LCD driver circuit temporarily per every common period. Normal / reverse display, display ON/OFF, and display all on command are done by controlling data in this latch. And no data within display RAM changes.
(15)
(16)
- 35 -
HM17CM4096
(17) EXAMPLE OF LCD DRIVING (NORMAL MODE, 1/163 DUTY, BLACK & WHITE DISPLAY MODE)
163
162
163
COM1 CL
SEG0
SEG1
SEG2
FLM
FR VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
COM0
COM1
SEG0
SEG1
Remark ) when 1/163 duty, the status of COM/SEG at 163rd driving sequence. COM : all no selection SEG : same with 162 line data output
162
1
234
5
1
234
5
162
163
COM0
1
- 36 -
HM17CM4096
(18) LCD DRIVER CIRCUIT This drive circuit generates four levels of LCD drive voltage. The circuit has 384 segment outputs and 162 common outputs and outputs combined display data and FR signal. The common drive circuit that has shift register and outputs common scan signals sequentially. (19) OSCILLATOR CIRCUIT HM17CM4096 has the CR oscillator. The output of oscillator is used as the timing signal source of display and boosting clock to the booster. If external clock is used, feed the clock to OSC1 pin or connect resistor between OSC1 and OSC2. And feedback resistance with command can set the inner oscillator circuit of HM17CM4096. The frame frequency can be altered by changed oscillator frequency according to feedback resistance length set value. To get optimum frame frequency, please check LCD and then set the frequency of oscillator. (20) POWER SUPPLY CIRCUIT This block generates the voltages necessary for driving LCD panel. The power supply circuit consists of voltage boosting circuit and voltage converting circuit and generates the voltages (VLCD, V1, V2, V3, V4. ) for LCD driving. For large panel driving, it's preferable to use external voltage source rather than to use built-in power supply circuit for good image quality. When using external voltage source, disable the built-in power supply circuit(AMPON, DCON=`00'), supply the VLCD, V1, V2, V3, V4 and VOUT externally and open the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VREF, VREG, VEE terminals. According to power supply circuit control command input, the power supply circuit can be enabled partially. External power supply and partial inner power circuit can be used together. Refer to the next table.
DCON AMPON
1. All the built-in boosting circuit, converting circuit is not used. Open the ,C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6-, VREF, VREG, VEE terminals, LCD driving voltage should be applied externally. 2.Only the Boosting circuit is not used. Open the C1+,C1-,C2+,C2-,C3+,C3-,C4+,C4-,C5+,C5-,C6+,C6-, VOUT terminals, The power for converting circuit must be supplied through VOUT terminal and the reference voltage must be supplied by VREF terminal. 3.The conditions between VOUT, VLCD, V1, V2, V3, and V4 are VOUT VLCD V1 V2 V3 V4 VSS.
y
y y
0 0 1
0 1 1
Boosting circuit Disable Disable Enable
Converting circuit disable enable enable
External voltage input VOUT, VLCD, V1, V2, V3, V4 common VOUT common -
remark 1,3 2,3 -

- 37 -
HM17CM4096
(21) VOLTAGE BOOSTING CIRCUIT By connecting capacitor CA1 between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+ and C4-, C5+ and C5- , C6+ and C6-, VOUT and VSS , n-time boosted voltage of VEE - VSS can be generated through VOUT port. The boosting coefficient can be set by command and 2-times/ 3-times / 4-times/ 5-times/ 6-times/ 7-times boosted voltage is output through VOUT port.
At application, specific boosting coefficient is used, refer to the following description. At 2-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , and open C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6- terminals. At 3-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , C2+ and C2- , and open C3+,C3-, C4+, C4-, C5+, C5-, C6+, C6- terminals. At 4-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , C2+ and C2- , C3+ and C3- , and open C4+, C4-, C5+, C5-, C6+, C6- terminals At 5-times/ 6-times/ 7-times boosting are same structures with upper case.
Special care should be taken so that the voltage of VOUT would not exceed 18V MAX. VOUT voltage exceeding 18V can cause malfunction and reliability problem.
VOUT=17.5V VOUT=9V
VEE=3V VSS=0V 3-times boosting
VEE=2.5V VSS=0V 7-times boosting
(22) ELECTRIC VOLUME The electric volume is within voltage converting circuit and the brightness of LCD can be controlled by adjusting VLCD level with command. The LCD driving voltage VLCD is generated by selecting 1 level within 128 step electric volume controlled levels by setting 7 bit electric volume register.
(23)
VOLTAGE REGULATOR CIRCUIT The voltage regulator circuit is within voltage converting circuit and generates regulated voltage using VREF input with magnification by adjusting internal resistor. The generated voltage by voltage regulator is output at VREG terminal. Even though boosted voltage variation, generated regulator voltage is stable because boosting voltage level is higher than the amplified regulator voltage VREG . And so, stable voltage level can be generated even if there is load variation. VREG is used as input voltage of electric volume circuit to generate LCD driving voltage.
- 38 -
HM17CM4096
(24) REFERENCE VOLTAGE GENERATION CIRCUIT The reference voltage generation circuit is within voltage converting circuit. This circuit generates reference voltage VBA terminal for using at regulator circuit through. output voltage level from VBA terminal is as following description. VBA = VEE x 0.9 The LCD driving voltages can be made by applying reference voltage to reference voltage input terminal VREF .
The
(25)
LCD DRIVING VOLTAGE GENERATION CIRCUIT The generation circuit of LCD driving voltage is within voltage converting circuit and generates voltages VLCD, V1, V2, V3, V4 by resistively dividing VLCD into 4 levels. The bias ratio of LCD driving voltages can be one of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10, 1/11, 1/12. When using built-in power supply circuit, you should connect voltage stabilization capacitor CA2 at each of LCD power terminals. There is need for selecting the coefficient of capacitor CA2 after display the LCD. When using external voltage supply, disable the built-in power supply circuit(AMPON, DCON=`00'), supply the VOUT, VLCD, V1, V2, V3, V4 voltages externally and open the C1+ , C1- , C2+ , C2- , C3+ , C3- , C4+ , C4- , C5+ , C5- , C6+ , C6- , VEE , VREF , VREG terminals. When using external voltage source and parts of built-in voltage converting circuit, the terminals of C1+ , C1- , C2+ , C2- , C3+ , C3- , C4+ , C4- , C5+ , C5- , C6+ , C6- should be open because boosting circuit is not activated, you should supply reference voltage through VREF terminal and the voltage for voltage converting circuit at VOUT . Connecting stabilization capacitor CA3 at VREG terminal is recommended.
- 39 -
HM17CM4096
internal power circuit / internal reference voltage generating circuit are activated case.(7 times boosting) VDD VDD VEE VBA VREF CA3 VSS CA1 VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT internal power circuit is not used case VDD
VDD VEE VBA VREF VREG C1 C1+ C2C2+ C3C3+
CA1
CA1
CA1
HM17CM4096
C4C4+ C5C5+ C6C6+ VOUT
HM17CM4096
CA1
CA1
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VLCD V1 V2 V3 V4
VLCD V1 Extnal power V2 circuit V3 V4
VLCD V1 V2 V3 V4
value CA1 CA2 CA3 cautiony
1.0 ~ 4.7F 1.0 ~ 2.2F 0.1F Please use B grade capacitor.
- 40 -
HM17CM4096
Internal power circuit is used case. Reference voltage input from outside . (7 times boosting)
Internal power circuit is Temperature compensation thermistor . (7 times boosting ) VDD
used case. by external
VDD
VDD VEE VBA VREF
thermistor
VDD VEE VBA VREF
CA3 VSS CA1
VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT
CA3 VSS CA1
VREG C1C1+ C2C2+ C3C3+ C4C4+ C5C5+ C6C6+ VOUT
CA1
CA1
CA1
CA1
CA1
HM17CM4096
CA1
HM17CM4096
CA1
CA1
CA1
CA1
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
CA1 VSS CA2 CA2 CA2 CA2 VSS CA2
VLCD V1 V2 V3 V4
VLCD V1 V2 V3 V4
value CA1 CA2 CA3 caution
1.0 ~ 4.7F 1.0 ~ 2.2F 0.1F Please use B grade capacitor.
- 41 -
HM17CM4096
Internal power circuit is used case. (boosting circuit is not used, VOUT is supplied from outside)
VDD
VDD VEE VBA VREF
CA3 VSS
VREG C1 C1 + C2 C2 + C3 C3 + C4 C4 + C5 C5 + C6 -
HM17CM4096
External power circuit
C6 + VOUT
CA2 CA2 CA2 CA2 VSS CA2
VLCD V1 V2 V3 V4
value CA1 CA2 CA3 caution
1.0 ~ 4.7F 1.0 ~ 2.2F 0.1F Please use B grade capacitor.
- 42 -
HM17CM4096
PARTIAL DISPLAY FUNCTION
HM17CM4096 can realize the partial display at graphic display area on LCD panel. Partial display is used with lower duty than normal state at driving. And so, HM17CM4096 can drive the LCD panel with lower bias ratio, lower boosting times and lower LCD driving voltages, and that can drive the LCD panel with lower power consumption. This function is suitable for calendar or clock display at mobile information apparatus.
PARTIAL DISPLAY IMAGE hynix LCD DRIVER Low Power and Low Voltage Normal display LCD DRIVER
partial display
The next sequence should be followed carefully to realize partial display function.
Any display states
DISPLAY OFF(ON/OFF="0")
built-in power source OFF(DCON="0", AMPON="0")
WAIT
Built-in power source ON(DCON="1", AMPON="1")
WAIT
Display ON(ON/OFF="1")
Partial display state
Setting the display-related function

Setting the power supply circuit
boosting coefficient electric volume bias ratio
duty ratio display start line setting display start command and so on.
- 43 -
HM17CM4096
When using partial display function, the display duty can be selected among 1/16, 1/24, 1/32, 1/40, 1/48, 1/56, 1/64, 1/72, 1/80, 1/96, 1/112, 1/128, 1/133, 1/144, 1/160, 1/163 by setting the LCD duty set command. The display states such as LCD driving bias ratio, LCD Driving voltage, electric volume setting value, boosting coefficient should be optimized to the selected LCD and display duty. (26) DISCHARGE CIRCUIT The discharge circuit of voltage(VLCD, V1~V4) stabilization capacitor is built in the HM17CM4096. To discharge the capacitors, set the DIS register to "1" or set the RES terminal to "0". When built-in power supply circuit is used, built-in power supply circuit should be disabled before discharging of the capacitor is executed. When external power supply(VLCD, V1~V4, VOUT) is used, external power supply should be turned off before discharging of the capacitor is executed. Do not turn on the internal power supply and external power supply (VLCD, V1~V4, VOUT) during discharging is executed. (27) RESET CIRCUIT HM17CM4096 is initialized as following description when RES terminal is set to "L". INITIAL SETTING CONDITION (default setting)
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. display RAM :unknown X address :00H set Y address :00H set display start line :1 line value 0H display ON/OFF :display OFF positive/negative :positive display duty ratio :1/163 n line inversion :n inversion disable COM shift direction :COM0 COM161 increment mode :increment OFF REF mode :positive data SWAP mode :OFF electric volume :(0, 0, 0, 0, 0, 0, 0) power circuit :OFF display mode:gradation display mode bias ratio :1/9 bias gradation palette 0 :(0, 0, 0, 0, 0) gradation palette 1 :(0, 0, 1, 0, 1) gradation palette 2 :(0, 1, 0, 1, 0) gradation palette 3 :(0, 1, 1, 1, 0) gradation palette 4 :(1, 0, 0, 0, 1) gradation palette 5 :(1, 0, 1, 0, 1) gradation palette 6 :(1, 1, 0, 1, 0) gradation palette 7 :(1, 1, 1, 1, 1) gradation mode :variable mode GLSB :"0" RAM data length :8 bit mode discharge register :"0"
Usually RES terminal is connected reset terminal of CPU, so that the chip can be initialized simultaneously with CPU. HM17CM4096 should be initialized when the power is on.
- 44 -
HM17CM4096
(28) SUPPLYING POWER AND ON/OFF SEQUENCE Special care should be taken to the next notice. Supplying the power at LCD driving voltage terminal when the logic VDD is floating can cause over-current and damage the IC (28-1)
WHEN USING EXTERNAL POWER SUPPLY
power ON sequence Reset the IC after supplying the logic power at VDD terminal, and then turn on the LCD driving voltage at the terminals (VLCD, V1, V2, V3, V4). And when internal voltage converter is used, reset the IC after supplying the logic power at VDD terminal, and then supply power to VLCD terminal. power OFF sequence
(28-2) WHEN USING BUILT-IN POWER SUPPLY CIRCUIT power ON sequence

Execute HALT command or reset the IC to turn off the outputs of LCD driving output port, and then turn off the LCD driving voltage after logic power OFF. Inserting series resistor of 50 ~100 or fuse at VLCD or VOUT terminal (when only internal voltage converting circuit is used) is recommended to prevent over-current. This series resistor should be selected carefully because image quality can be dependent on.
Reset the IC after supplying the logic power at VDD terminal or after supplying power through voltage common port (VEE) of boosting voltage generation and then operate internal power circuit by command. And when internal voltage converter is used, reset the IC after supplying the logic power at VDD terminal, and then supply power to VLCD terminal. You should turn on the display after the output level of internal power module is set. If you do not keep this sequence, LCD can display wrong data. power OFF sequence To make off state of LCD driving output, cut the source to voltage common port (VEE) of boosting voltage generation, the logic power at VDD terminal after reset the IC by HALT command. If VEE, and VDD are supplied from different power source, VEE terminal should be turned on/off during VDD terminal voltage maintain voltage level specified in specification sheet. Specially, when turn off the power, after cut the source to voltage common port (VEE), and then turn off the logic power at VDD terminal after the voltage levels of VEE, VOUT, VLCD, V1~V4 become under LCD on voltage(LCD threshold voltage)level.
- 45 -
HM17CM4096
(29) COMMAND SETTING EXAMPLE (29-1) initial setting
VDD, VEE-VSS power ON
Power stable
RESET input
WAIT
Function setting by command (user setting|
End of initial setting
(notice) If the voltage level of VEE and VDD are different, VDD should be inputted first.
(29-2)
DATA DISPLAY
End of initialization
Data display
Function setting by command (user setting)
Function setting by command (user setting|
Function setting by command (user setting)

Function setting by command (user setting|
electric volume code set bias ratio set
power control set (DCON="1", AMPON="1")
display start line set increment mode set X address set Y address set
display data write
display ON/OFF command set(ON/OFF="1")
- 46 -
HM17CM4096
(29-3) POWER OFF
Any operation states HALT command set or reset operation (all LCD driver output is VSS level) Discharge command set (discharge of VLCD, V1~V4 capacitor)
Function setting by command (user setting
WAIT
VEE, VDD-VSS power OFF
Before turning off the power, be sure to execute HALT or RESET command to make LCD driver output OFF state. Please, discharge the capacitors that connected to VLCD, V1, V2, V3,V4 before power OFF.
- 47 -
HM17CM4096
(30) INSTRUCTION
INSTRUCTION TABLE (1)
CODE(80 series I/F) INSTRUCTION CS X address(lower) X address(upper) Y address(lower) Y address(upper) display start line set (lower) display start line set (upper) N line inversion set (lower) N line inversion set (upper) display control (1) 0 0 0 0 0 0 0 0 0 RS 1 1 1 1 1 1 1 1 1 RD WR RE2 RE1 RE0 D7 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D6 0 0 0 0 1 1 1 1 0 D5 D4 D3 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 D2 D1 D0 RE flag Register address Control address function
AX3 AX2 AX1 AX0 Write in to display RAM * AX6 AX5 AX4

AY7 AY6 AY5 AY4 LA3 LA2 LA1 LA0 RAM Y address setting corresponds to scan start LA7 LA6 LA5 LA4 line of common driver. N3 N7 N2 N6 N1 N5 N0 N4 quantity setting inversion of line
SHIFT: common shift direction set,
SHI MO FT N NLI N
ALL ON/ MON: BW/gradation display, ON OFF ALLON: all on , SWA REF P AXI
display control (2)
0
1
1
0
0
0
0
1
0
0
1 REV
increment control
0
1
1
0
0
0
0
1
0
1
0 WIN AIM AYI
power control
0 0 0 0 0
1 1 1 1 1
1 1 1 1 1
0 0 0 0 0
0 0 0 0 0/1
0 0 0 0 0/1
0 0 0 0 0/1
1 1 1 1 1
0 1 1 1 1
1 0 0 1 1
1
AMP HAL DCO ACL ON T N
ON/OFF: display ON/OFF control REV: display positive / negative, NLIN: n line inversion ON/OFF, SWAP: display data swap, REF: segment positive / negative WIN: window selection, AIM: increment timing selection, AYI:Y increment, AXI:X increment AMPON: internal OP Amp. ON, HALT: power save DCON: boosting circuit ON, ACL: reset
LCD duty set boosting coefficient set bias ratio set RE register set
0 DS3 DS2 DS1 DS0 LCD driver duty ratio set 1 0 1 * * VU2 VU1 VU0 Boosting times set B2 B1 B0 LCD drive bias set
TST RE2 RE1 RE0 RE flag set
Notice 1) * mark is Don't Care Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input. But electric volume is effective after upper and lower register setting.
(c)
AY3 AY2 AY1 AY0
RAM Y
- 48 -
HM17CM4096
INSTRUCTION TABLE (2)
CODE(80 series I/F) INSTRUCTION CS Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) RE register set Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) Gradation palette set ( lower ) Gradation palette set ( upper ) RE register set R0/R8 R0/R8 R1/R9 R1/R9 R2/R10 R2/R10 R3/R11 R3/R11 R4/R12 R4/R12 R5/R13 R5/R13 R6/R14 R6/R14 R7/R15 R7/R15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 G0/G8 G0/G8 G1/G9 G1/G9 G2/G10 G2/G10 G3/G11 G3/G11 G4/G12 G4/G12 G5/G13 G5/G13 G6/G14 G6/G14 G7/G15 G7/G15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RD WR RE2 RE1 RE0 D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0/1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 D5 D4 D3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 D2 D1 D0 RE flag Register address Control address function PR0 PR0 PR0 PR0 Set gradation palette R0 or 3 2 1 0 R8 PR0 * * * 4 PR1 PR1 PR1 PR1 Set gradation palette R1 or 3 2 1 0 R9 PR1 * * * 4 PR2 PR2 PR2 PR2 Set gradation palette R2 or 3 2 1 0 R10 PR2 * * * 4 PR3 PR3 PR3 PR3 Set gradation palette R3 or 3 2 1 0 R11 PR3 * * * 4 PR4 PR4 PR4 PR4 Set gradation palette R4 or 3 2 1 0 R12 PR4 * * * 4 PR5 PR5 PR5 PR5 Set gradation palette R5 or 3 2 1 0 R13 PR5 * * * 4 PR6 PR6 PR6 PR6 Set gradation palette R6 or 3 2 1 0 R14 PR6 * * * 4 PR7 PR7 PR7 PR7 3 2 1 0 Set gradation palette R7 or PR7 R15 * * * 4 TST RE2 RE1 RE0 RE flag set PG0 PG0 PG0 PG0 3 2 1 0 Set gradation palette G0 PG0 or G8 * * * 4 PG1 PG1 PG1 PG1 3 2 1 0 Set gradation palette G1 PG1 or G9 * * * 4 PG2 PG2 PG2 PG2 3 2 1 0 Set gradation palette G2 PG2 or G10 * * * 4 PG3 PG3 PG3 PG3 3 2 1 0 Set gradation palette G3 PG3 or G11 * * * 4 PG4 PG4 PG4 PG4 3 2 1 0 Set gradation palette G4 PG4 or G12 * * * 4 PG5 PG5 PG5 PG5 3 2 1 0 Set gradation palette G5 PG5 or G13 * * * 4 PG6 PG6 PG6 PG6 Set gradation palette G6 3 2 1 0 or G14 PG6 * * * 4 PG7 PG7 PG7 PG7 3 2 1 0 Set gradation palette G7 PG7 or G15 * * * 4 TST RE2 RE1 RE0 RE flag set
Notice 1) * mark is Don't Care Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input.
- 49 -
HM17CM4096
But electric volume is effective after upper and lower register setting.
INSTRUCTION TABLE (3)
CODE(80 series I/F) INSTRUCTION CS Gradation palette B0/B8 set ( lower ) Gradation palette B0/B8 set ( upper ) Gradation palette B1/B9 set ( lower ) Gradation palette B1/B9 set ( upper ) Gradation palette B2/B10 set ( lower ) Gradation palette B2/B10 set ( upper ) Gradation palette B3/B11 set ( lower ) Gradation palette B3/B11 set ( upper ) Gradation palette B4/B12 set ( lower ) Gradation palette B4/B12 set ( upper ) Gradation palette B5/B13 set ( lower ) Gradation palette B5/B13 set ( upper ) Gradation palette B6/B14 set ( lower ) Gradation palette B6/B14 set ( upper ) Gradation palette B7/B15 set ( lower ) Gradation palette B7/B15 set ( upper ) RE register set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RD WR RE2 RE1 RE0 D7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0/1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 D6 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 D5 D4 D3 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 D2 D1 D0 B0 or RE flag Register address Control address function PB0 PB0 PB0 PB0 Set gradation palette 3 2 1 0 B8 PB0 * * * 4 PB1 PB1 PB1 PB1 Set gradation palette 3 2 1 0 B9 PB1 * * * 4 PB2 PB2 PB2 PB2 Set gradation palette 3 2 1 0 B10 PB2 * * * 4 PB3 PB3 PB3 PB3 Set gradation palette 3 2 1 0 B11 PB3 * * * 4 PB4 PB4 PB4 PB4 Set gradation palette 3 2 1 0 G12 PB4 * * * 4 PB5 PB5 PB5 PB5 Set gradation palette 3 2 1 0 B13 PB5 * * * 4 PB6 PB6 PB6 PB6 Set gradation palette 3 2 1 0 B14 PB6 * * * 4 PB7 PB7 PB7 PB7 3 2 1 0 Set gradation palette PB7 B15 * * * 4 TST RE2 RE1 RE0 RE flag set
B1 or
B2 or
B3 or
B4 or
B5 or
B6 or
B7 or
Notice 1) * mark is Don't Care Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input. But electric volume is effective after upper and lower register setting.
- 50 -
HM17CM4096
INSTRUCTION TABLE (4)
INSTRUCTION Display start command set Display signal output set CODE(80 series I/F) CS 0 0 RS 1 1 RE flag Register address D6 1 1 Control address D2 D1 D0 RD WR RE2 RE1 RE0 D7 1 1 0 0 1 1 0 0 0 0 0 0 D5 D4 D3 1 1 function Common driver scan start set
Control of outputs status of CKL CL FLM FR
0 SC3 SC2 SC1 SC0 1 * * *
SON 0CKL CL FLM FR="L"(default)
1CKL CL FLM FR="H" PWM variable 16 /fixed 8 gray mode selection C256 256 color Mode ON/OFF(default : OFF) FDC boost clock control HSW high speed write in at 8 bit access mode ABS effective 12 bit RAM selection CKS oscillator selection WLS RAM access length 8 /16 bit

Display selection control
0
1
1
0
1
0
0
1
0
0
0
PW M
C25 FDC FDC 6 1 2
RAM data length
0
1
1
0
1
0
0
1
0
0
1
HS W
ABS CKS WLS
Electric volume control (lower) Electric volume control (upper) Address set for internal address reading Oscillator Rf control discharge RE register set Window end X address set (lower) Window end X address set (upper) Window end Y address set (lower) Window end Y address set (upper) Line inversion start address (lower) Line inversion start address (upper) Line inversion end address (lower) Line inversion end address (upper) Line inversion control Gradation palette setting selection PWM mode control RE register set
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0/1 1 1 1 1 1 1 1 1 1 1 1 0/1
0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0/1
0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 0/1
1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 *
DV3 DV6 DV5 DV4
DV2
D
Address for register Internal register read out read * RF2 RF1 RF0 RF oscillator Rf selection Cap. Of VLCD! V1 V4 * * * DIS discharge TST RE2 RE1 RE0 RE flag set X end address under EX3 EX2 EX1 EX0 window mode * EX6 EX5 EX4 Y end address window mode under
"
EY3 EY2 EY1 EY0 EY7 EY6 EY5 EY4 LS3 LS2 LS1 LS0 LS7 LS6 LS5 LS4 LE3 LE2 LE1 LE0 LE7 LE6 LE5 LE4 * * BT
Start line address set under line inversion mode
End line address set under line inversion mode
LRE BT: blink type set V LREV: line inversion ON/OFF Upper/lower 8 gradation 1 * * * PS palette PW PW PW PW 0 PWM mode selection MS MA MB MC 1 TST RE2 RE1 RE0 RE flag set
Notice 1) * mark is Don't Care Notice 2) The commands that upper/lower register settings are demanded are effective at the point of commands input. But electric volume is effective after upper and lower register setting.
- 51 -
HM17CM4096
s RELATION BETWEEN PS REGISTER AND GRADATION PALETTE (1)
Gradat ion palette R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 G0 G1 G2 G3 G4 G5 G6 G7 Upper / lower Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper RE register RE2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RE1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 RE0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 PS register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting register address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 02h 03h Gradation palette control register D3 PR03 * PR13 * PR23 * PR33 * PR43 * PR53 * PR63 * PR73 * PR03 * PR13 * PR23 * PR33 * PR43 * PR53 * PR63 * PR73 * PG03 * PG13 * PG23 * PG33 * PG43 * PG53 * PG63 * PG73 * D2 PR02 * PR12 * PR22 * PR32 * PR42 * PR52 * PR62 * PR72 * PR02 * PR12 * PR22 * PR32 * PR42 * PR52 * PR62 * PR72 * PG02 * PG12 * PG22 * PG32 * PG42 * PG52 * PG62 * PG72 * D1 PR01 * PR11 * PR21 * PR31 * PR41 * PR51 * PR61 * PR71 * PR01 * PR11 * PR21 * PR31 * PR41 * PR51 * PR61 * PR71 * PG01 * PG11 * PG21 * PG31 * PG41 * PG51 * PG61 * PG71 * D0 PR00 PR04 PR10 PR14 PR20 PR24 PR30 PR34 PR40 PR44 PR50 PR54 PR60 PR64 PR70 PR74 PR00 PR04 PR10 PR14 PR20 PR24 PR30 PR34 PR40 PR44 PR50 PR54 PR60 PR64 PR70 PR74 PG00 PG04 PG10 PG14 PG20 PG24 PG30 PG34 PG40 PG44 PG50 PG54 PG60 PG64 PG70 PG74
- 52 -
HM17CM4096
s RELATION BETWEEN PS REGISTER AND GRADATION PALETTE (2)
Gradat ion palette G8 G9 G10 G11 G12 G13 G14 G15 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 Upper / lower Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper Lower Upper RE register RE2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 RE1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 RE0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 PS register 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Setting register address 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 02h 03h 04h 05h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 00h 01h 02h 03h 04h 05h Gradation palette control register D3 PG03 * PG13 * PG23 * PG33 * PG43 * PG53 * PG63 * PG73 * PB03 * PB13 * PB23 * PB33 * PB43 * PB53 * PB63 * PB73 * PB03 * PB13 * PB23 * PB33 * PB43 * PB53 * PB63 * PB73 * D2 PG02 * PG12 * PG22 * PG32 * PG42 * PG52 * PG62 * PG72 * PB02 * PB12 * PB22 * PB32 * PB42 * PB52 * PB62 * PB72 * PB02 * PB12 * PB22 * PB32 * PB42 * PB52 * PB62 * PB72 * D1 PG01 * PG11 * PG21 * PG31 * PG41 * PG51 * PG61 * PG71 * PB01 * PB11 * PB21 * PB31 * PB41 * PB51 * PB61 * PB71 * PB01 * PB11 * PB21 * PB31 * PB41 * PB51 * PB61 * PB71 * D0 PG00 PG04 PG10 PG14 PG20 PG24 PG30 PG34 PG40 PG44 PG50 PG54 PG60 PG64 PG70 PG74 PB00 PB04 PB10 PB14 PB20 PB24 PB30 PB34 PB40 PB44 PB50 PB54 PB60 PB64 PB70 PB74 PB00 PB04 PB10 PB14 PB20 PB24 PB30 PB34 PB40 PB44 PB50 PB54 PB60 PB64 PB70 PB74
- 53 -
HM17CM4096
s ABSOLUTE MAXIMUM RATING
ITEM supply voltage (1) supply voltage (2) supply voltage (3) supply voltage (4) supply voltage (5) supply voltage (6) input voltage Storage temperature *1 SYMBOL VDD VEE VOUT VREG VLCD V1, V2, V3, V4 VI Tstg CONDITION PORT VDD VEE VOUT VREG VLCD V1, V2, V3, V4 *1 RATINGS -0.3 ~ +4.0 -0.3 ~ +4.0 -0.3 ~ +20.0 -0.3 ~ +20.0 -0.3 ~ +20.0 -0.3 ~ VLCD + 0.3 -0.3 ~ VDD + 0.3 -45 ~ +125 UNIT V V V V V V V C
VSS(0V) reference Ta = +25C
D0~D15, CS, RS, M/S, RD, WR, OSC1, LP, FLM, FR, CLK, RES, TEST port
s RECOMMENDED OPERATING CONDITIONS
ITEM supply voltage SYMBOL VDD1 VDD2 VEE VLCD VOUT VREG VREF Topr PORT VDD VEE VLCD VOUT VREG VREF MIN 1.7 2.4 2.4 5 TYP MAX 3.3 3.3 3.3 18.0 18.0 VOUT x 0.9 3.3 85 UNIT REMARK V *1 V *2 V *3 V *4 V V V *5 C
Recommended operating voltage Operation temperature *1 *2 *3 *4 *5
2.1 -30
The case when internal reference voltage generation circuit (VBA output) is not used. The voltage compare to VSS port. The case when internal reference voltage generation circuit (VBA output) is used. The voltage compare to VSS port. When the boosting circuit is used, supply voltage VEE should be used within the limit. When driving LCD panel by use of internal boosting circuit, it is possible to short VDD and VEE. Please keep the relation, VSS < V4 < V3 < V2 < V1 < VLCDVOUT. When the internal voltage regulator circuit is used, reference voltage VREF should be used within the limit. Please keep the relation VREFVEE .
- 54 -
HM17CM4096
s ELECTRICAL CHARACTERISTICS
*
DC Characteristics 1 ITEM
SYMBOL
High level input voltage Low level input voltage High level output voltage Low level output voltage High level output voltage Low level output voltage Input leakage current Output leakage current
VIH VIL VOH1 VOL1 VOH2 VOL2 ILI ILO RON1 ISTB fOSC1 fOSC2 fOSC3 fr1 fr2 fr3 VOUT IDD1 IDD3 IDD5 IDD7 IDD9 IDD11 IDD13 IDD15 VBA VREG V2 V3 VD12 VD34 |#
Unless otherwise noted VSS = 0V, CONDITION MIN 0.8 VDD 0 IOH = -0.4mA VDD - 0.4 IOL = 0.4mA IOH = -0.1mA VDD - 0.4 IOL = 0.1mA VI = VSS or VDD -10 VI = VSS or VDD -10 VON| = 0.5V
VLCD = 10V
LCD driver output ON resistance Static current Oscillator frequency oscillator frequency by External resistor Boosting output voltage
Current consumption (1) Current consumption (2) Current consumption (3) Current consumption (4) Current consumption (5) Current consumption (6) Current consumption (7) Current consumption (8)
VLCD = 6V VDD = 3V FFL = "0"
(normal mode)
VDD = +1.7~+3.3V, Ta = -30~+85C UNIT PORT TYP MAX VDD V *1 0.22 VDD V V *2 0.4 V V *3 0.4 V 10 *4 A 10 *5 A 1 2 *6 k 2 4 763 172 25 750 185 27.2 15 900 203 29.5 A kHz *7 *8 *9 *10 *11
CS=VDD, Ta=25C VDD = 3V Ta = 25C
Rf=10k Rf=51k Rf=390k
625 141 20.5
kHz
N x boosting (N=2~7) RL =500k (between VOUT ,VSS) VDD = 2.5V
7 x boosting (all ON)
N * VEE * 0.95 870 1060 760 930 520 650 360 450
$
V 1300 1590 1140 1400 780 980 540 680 (0.9 VEE) 1.02
&
*12
VDD = 2.5V 7x boosting
(cross check)
VDD = 3.0V 6 x boosting (all ON) VDD = 3.0V 6x boosting
(cross check)
VDD = 3.0V5 x boosting
(all ON)
A
*13
VDD = 3.0V 5x boosting
(cross check)
VDD = 3.0V 4 x boosting
(all ON)
VDD = 3.0V 4x boosting
(cross check)
$ &
VBA output voltage VREG output voltage
VEE = 2.4~3.3V VEE = 2.4~3.3V VREF = 0.9 VEE N boosting (N=2~7)
$ %
(0.9 VEE) 0.98
&
0.9 VEE
V V mV mV mV mV
*14 *15
(VREF N) (VREF N) (VREF x N) 0.97 1.03 -100 -100 -30 -30 0 0 0 0
&
Output voltage
+100 +100 +30 +30
*16
- 55 -
HM17CM4096
Applied port (* Remark Solves) D0~D15, CS, RS, M/S, RD, WR, P/S, SEL68, CLK, CL, FLM, FR, RES ports D0~D15 ports CL, FLM, FR, CLK ports CS, RS, M/S, SEL68, RD, WR, P/S, RES, OSC1 ports applicable at D0~D15, CL, FLM, FR, CLK = high impedance state SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127, COM0~COM79, COMI0, COMI1 ports resistance when being supplied 0.5V between each output ports and power port (VLCD, V1, V2, V3, V4) applicable under bias ratio = 1/9 *7 VDD ports VDD current when source clock is stopped, chip selection (CS=VDD) is non-selection state and no load. *8 oscillator frequency when internal oscillator circuit is used ( gradation display mode). applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = "000" *9 oscillator frequency when internal oscillator circuit is used ( fixed gradation display mode). applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = "000" *10 oscillator frequency when internal oscillator circuit is used ( BW display mode). applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = "000" *11 VDD 3 253 *12 VOUT port N x boosting (N=2~7). applicable under internal oscillator circuit and internal power circuit are ON state VEE = 2.4~3.3V, electric volume is MAX("1111111"). bias = 1/5~1/10, 1/82 duty, no load at LCD driver port. RL = 500k(between VOUT ,VSS), CA1= CA2=1.0F, CA3=0.1F, DCON="1", AMPON="1" *13 applicable under internal oscillator circuit and internal power circuit are ON state and no access from CPU. electric volume is "1111111". Display is all ON and cross check pattern display ( variable gradation display mode), and no load at LCD driver port. Test condition : VDD=VEE, VREF=0.9VEE, CA1=CA2=1.0F, CA3=0.1F, DCON="1", AMPON="1", NLIN="0", 1/82 duty. Ta=25 *14 VREG output voltage when VBA output is connected to VREF input, VREG gain is N=1. force VOUT=13.5V with DCON="0" *15 VREG port VEE= 2.4~3.3V, VREF= 0.9 VEE, bias= 1/5~1/10, 1/82 duty, electric volume is "1111111"5 Cross check pattern state and no load at LCD driver port. Boosting coefficient N is 2~7 times Test condition : CA1=CA2=1.0F, CA3=0.1F, DCON="1", AMPON="1", NLIN="0"5 *16 VLCD6 V16 V26 V36 V4 port VEE = 3.0V, VREF = 0.9 VEE, out=13.5 , bias = 1/5~1/10, electric volume is "1111111"5 Display OFF and no load at LCD drive port. Boosting coefficient N is 5 times. Test condition : CA2=1.0F, CA3=0.1F, DCON="0", AMPON="1"5
VLCD
@ 4 2 1 0 ) ( '
*1 *2 *3 *4 *5 *6
V4 VSS
B
C
V3
B
A
V1 V2
@
9
7
7
VD12 = VD34 =
-
8
- 56 -
HM17CM4096
s AC CHARACTERISTICS
*
SYSTEM BUS READ / WRITE TIMING (80 series CPU interface) tAS8 tAH8
(write timing) CS RS
WR
tWRLW8
tWRHW8 tDS8 tDH8
D0 D15 tCYC8 (VDD=2.53.3V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns ns ns WR D0 D15
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 90 35 35 30 5
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 160 70 70 40 5
(VDD=2.22.5V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns ns ns WR D0 D15
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
notice)
SYMBOL tAH8 tAS8 tCYC8 tWRLW8 tWRHW8 tDS8 tDH8
CONDITION
MIN. 0 0 180 80 80 70 10
MAX.
(VDD=1.7~2.2, Ta=-30+85C) UNIT PORT ns CS ns RS ns ns ns ns ns WR D0 D15
All timing reference is 20% and 80% of VDD and 80%.
- 57 -
HM17CM4096
D
read timingE tAS8 CS RS tAH8
RD
tWRLR8 tWRHR8 tRDH8
D0 D15 tRDD8 tCYC8 (VDD=2.53.3V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 60 0 ns ns RD D0 D15
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8
CONDITION
MIN. 0 0 180 80 80
CL = 15 pF
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8
CONDITION
MIN. 0 0 180 80 80
(VDD=2.22.5V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 60 ns ns RD D0 D15
CL = 15 pF 0
ITEM Address hold timing Address setup timing System cycle timing Write "L" pulse width Write "H" pulse width Data setup timing Data hold timing
notice)
SYMBOL tAH8 tAS8 tCYC8 tWRLR8 tWRHR8 tRDD8 tRDH8
CONDITION
MIN. 0 0 250 120 120
(VDD=1.72.2V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 110 ns ns RD D0 D15
CL = 15 pF 0
All timing reference is 20% and 80% of VDD and 80%.
- 58 -
HM17CM4096
*
SYSTEM BUS READ / WRITE TIMING (68 series CPU interface)
(write timingF tAS6 CS RS R/W (WR) tAH6
tELW6 E (RD) tEHW6 tDS6 tDH6
D0 D15 tCYC6 ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW6 tDS6 tDH6 SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW8 tDS6 tDH6
CONDITION CONDITION
MIN. 0 0 90 35 35 40 5 MIN. 0 0 160 70 70 50 5
(VDD=2.53.3V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns ns ns E D0 D15
(VDD=2.22.5V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns ns ns E D0 D15
ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing
notice)
SYMBOL tAH6 tAS6 tCYC6 tELW6 tEHW8 tDS6 tDH6
CONDITION
MIN. 0 0 180 80 80 70 10
(VDD=1.72.2V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns ns ns E D0 D15
All timing reference is 20% and 80% of VDD and 80%.
- 59 -
HM17CM4096
(read timing) CS RS tAS6 tAH6
R/W (WR) tELR6 E (RD) tRDH6 D0 D15 tRDD6 tCYC6 (VDD=2.53.3V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 70 0
CONDITION
tEHR6
ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR6 tRDD6 tRDH6 SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR8 tRDD6 tRDH6
CONDITION
MIN. 0 0 180 80 80
E D0 D15
CL = 15 pF
ns ns
MIN. 0 0 180 80 80
(VDD=2.22.5V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 70 ns ns E D0 D15
CL = 15 pF 0
ITEM Address hold timing Address setup timing System cycle timing Enable "L" pulse width Enable "H" pulse width Data setup timing Data hold timing
notice)
SYMBOL tAH6 tAS6 tCYC6 tELR6 tEHR8 tRDD6 tRDH6
CONDITION
MIN. 0 0 250 120 120
(VDD=1.72.2V, Ta=-30+85C) MAX. UNIT PORT ns CS ns RS ns ns ns 110 ns ns E D0 D15
CL = 15 pF 0
All timing reference is 20% and 80% of VDD and 80%.
- 60 -
HM17CM4096
*
SERIAL INTERFACE TIMING tCSS tCSH
CS
RS tASS SCL tSHW tCYCS tSLW tAHS
tDSS
tDHS
SDA (VDD=2.53.3V, Ta=-30+85C) MAX. UNIT PORT ns SCL ns ns ns RS ns ns SDA ns ns ns CS
ITEM Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address setup timing Address hold timing Data setup timing Data hold timing CS - SCL timing CS hold timing
SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH
CONDITION
MIN. 50 20 20 20 20 20 20 20 20
ITEM Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address setup timing Address hold timing Data setup timing Data hold timing CS - SCL timing CS hold timing
SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH
CONDITION
MIN. 50 20 20 20 20 20 20 20 20
(VDD=2.22.5V, Ta=-30+85C) MAX. UNIT PORT ns ns SCL ns ns RS ns ns SDA ns ns ns CS
ITEM Serial clock cycle SCL "H" pulse width SCL "L" pulse width Address setup timing Address hold timing Data setup timing Data hold timing CS - SCL timing CS hold timing
notice)
SYMBOL tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH
CONDITION
MIN. 80 35 35 35 35 35 35 35 35
(VDD=1.72.2V, Ta=-30+85C) MAX. UNIT PORT ns SCL ns ns ns RS ns ns SDA ns ns CS ns
All timing reference is 20% and 80% of VDD and 80%.
- 61 -
HM17CM4096
*
DISPLAY CONTROL TIMING (normal speed , FFL=0) tCLLW
tCLHW CL tDFLM
tDFLM FLM tDM
FR
OUTPUT TIMING ITEM FLM delay time FR delay time
SYMBOL tDFLM tFR
CONDITION
CL=15pF
MIN. 0 0
(VDD=2.43.3V, Ta=-30+85C) MAX. UNIT PORT 500 ns FLM 500 ns FR
OUTPUT TIMING ITEM FLM delay time FR delay time
notice)
SYMBOL tDFLM tFR
CONDITION
CL=15pF
MIN. 0 10
(VDD=1.72.4V, Ta=-30+85C) MAX. UNIT PORT 1000 ns FLM 1000 ns FR
All timing reference is 20% and 80% of VDD and 80%.
- 62 -
HM17CM4096
*
SOURCE CLOCK INPUT TIMING
tCKLW OSC1 tCKHW
ITEM OSC1 "H" pulse width (1) OSC1 "L" pulse width (1) OSC1 "H" pulse width (2) OSC1 "L" pulse width (2) OSC1 "H" pulse width (3) OSC1 "L" pulse width (3)
notice)
SYMBOL tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3
CONDITION
MIN. 0.525 0.525 2.45 2.45 16.9 16.9
(VDD=1.73.3V, Ta=-30+85C) MAX. UNIT PORT 0.800 OSC1 s 0.800 s 1 3.55 OSC1 s 3.55 s 2 24.4 OSC1 s 24.4 s 3
All timing reference is 20% and 80% of VDD and 80%.
1 2 3
applicable under gradation display , MON="0", PWM="0" applicable under fixed gradation display , MON="0",PWM="1" applicable under BW display , MON="1"
- 63 -
HM17CM4096
RESET INPUT TIMING
G
tRW RES tR
Internal status
resetting
Reset completion
ITEM Reset time RES "L" pulse width
SYMBOL tR tRW
CONDITION
MIN.
(VDD=2.43.3V, Ta=-30+85C) MAX. UNIT PORT 1.0 s s RES
10.0
ITEM Reset time RES "L"
notice)
SYMBOL tR tRW
CONDITION
MIN.
(VDD=1.72.4V, Ta=-30+85C) MAX. UNIT PORT 1.5 s s RES
pulse width
10.0
All timing reference is 20% and 80% of VDD and 80%.
- 64 -
HM17CM4096
connection with CPU a) 80 series CPU interface 1.7V ~ 3.3V
I H H
s APPLICATION EXAMPLE
referenceI
VCC (80 series CPU) b) 68 series CPU interface VCC (68 series CPU) VCC (CPU) GND GND
A0 A1 ~ A7 IORQ D0 ~ D7 RD WR RES 7 Decoder 8
RS CS
VDD
D0 ~ D7 RD WR RES VSS
GND Reset input
1.7V ~ 3.3V
A0 A1 ~ A15 15 VMA D0 ~ D7 E R/W RES Reset input Decoder 8
RS CS
VDD
D0 ~ D7 RD(E) WR(R/W) RES VSS
a) CPU connection with serial interface 1.7V ~ 3.3V
A0 A1 ~ A7 7 Decoder
RS CS
VDD
PORT1 PORT2 RES Reset input
SDA SCL RES VSS
- 65 -
HM17CM4096
Typical characteristic ITEM Basic delay time of gate
P P
CONDITION Ta=+25C, VSS=0V, VDD=3.0V
MIN
TYP 10
MAX
UNIT ns
IN/OUTPUT CIRCUIT STRUCTURE (a) input circuit 1 VDD port : CS, RS, RD, WR, SEL68 P/S, RES
I Input signal VSS(0V)
(b-1) in/out circuit 1 VDD I/O Input signal VSS(0V) VDD Output control signal Output signal VSS(0V) port : FLM, LP, FR, CLK
(b-2) in/out circuit 2 VDD port : D0~D15
I/O Input signal VSS(0V) VSS(0V) Input control signal VDD Output control signal Output signal VSS(0V)
- 66 -
HM17CM4096
(c) LCD driver output circuit VLCD
output control signal 1 output control signal 3
VLCD
VLCD
V1/V2
output control signal 2 output control signal 4
O
VSS(0V)
V3/V4
VSS(0V)
VSS(0V)
Port :
SEGA0~SEGA127 SEGB0~SEGB127 SEGC0~SEGC127 COM0~COM162

The details of this specification was written sincerely, but it is not a letter of guarantee of legal. Especially, the application circuit is just for reference. This specification do not guarantee that we did not use others patent or intellectural property.
- 67 -

▲Up To Search▲

Price & Availability of HM17CM4096

	To Download HM17CM4096 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .