FDB3632 / FDP3632 / FDI3632 April 2003 FDB3632 / FDP3632 / FDI3632 N-Channel PowerTrench(R) MOSFET 100V, 80A, 9m Features * r DS(ON) = 7.5m (Typ.), V GS = 10V, ID = 80A * Qg(tot) = 84nC (Typ.), VGS = 10V * Low Miller Charge * Low QRR Body Diode * UIS Capability (Single Pulse and Repetitive Pulse) * Qualified to AEC Q101 Formerly developmental type 82784 Applications * DC/DC converters and Off-Line UPS * Distributed Power Architectures and VRMs * Primary Switch for 24V and 48V Systems * High Voltage Synchronous Rectifier * Direct Injection / Diesel Injection Systems * 42V Automotive Load Control * Electronic Valve Train Systems D DRAIN (FLANGE) SOURCE DRAIN GATE SOURCE GATE DRAIN (FLANGE) SOURCE DRAIN GATE G TO-220AB FDP SERIES TO-263AB FDB SERIES DRAIN (FLANGE) TO-262AB FDI SERIES S MOSFET Maximum Ratings TC = 25C unless otherwise noted Symbol VDSS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID Continuous (TC < 111oC, VGS = 10V) Continuous (Tamb = 25oC, VGS = 10V, R JA = 43oC/W) Pulsed E AS PD TJ, TSTG Single Pulse Avalanche Energy (Note 1) Power dissipation Derate above 25oC Operating and Storage Temperature 80 12 Figure 4 393 310 2.07 -55 to 175 A A A mJ W W/oC o Ratings 100 20 Units V V C Thermal Characteristics RJC RJA RJA Thermal Resistance Junction to Case TO-220, TO-263, TO-262 Thermal Resistance Junction to Ambient TO-220, TO-262 (Note 2) Thermal Resistance Junction to Ambient TO-263, 1in copper pad area 2 0.48 62 43 o o o C/W C/W C/W This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Package Marking and Ordering Information Device Marking FDB3632 FDP3632 FDI3632 Device FDB3632 FDP3632 FDI3632 Package TO-263AB TO-220AB TO-262AA Reel Size 330mm Tube Tube Tape Width 24mm N/A N/A Quantity 800 units 50 units 50 units Electrical Characteristics TC = 25C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS IDSS IGSS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V VDS = 80V VGS = 0V VGS = 20V TC= 150oC 100 1 250 100 V A nA On Characteristics VGS(TH) rDS(ON) Gate to Source Threshold Voltage Drain to Source On Resistance V GS = VDS, ID = 250A ID=80A, VGS=10V ID =40A, VGS = 6V, ID=80A, VGS=10V, TC=175oC 2 0.0075 0.009 0.018 4 0.009 0.015 0.022 V Dynamic Characteristics CISS COSS CRSS Qg(TOT) Qg(TH) Qgs Qgs2 Qgd Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate Charge Threshold to Plateau Gate to Drain "Miller" Charge VDS = 25V, VGS = 0V, f = 1MHz VGS = 0V to 10V VGS = 0V to 2V VDD = 50V ID = 80A Ig = 1.0mA 6000 820 200 84 11 30 20 20 110 14 pF pF pF nC nC nC nC nC Resistive Switching Characteristics (VGS = 10V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time VDD = 50V, ID = 80A VGS = 10V, RGS = 3.6 30 39 96 46 102 213 ns ns ns ns ns ns Drain-Source Diode Characteristics VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge ISD = 80A ISD = 40A ISD = 75A, dISD/dt= 100A/s ISD = 75A, dISD/dt= 100A/s 1.25 1.0 64 120 V V ns nC Notes: 1: Starting TJ = 25C, L = 0.12mH, IAS = 75A. 2: Pulse Width = 100s (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Typical Characteristics TA = 25C unless otherwise noted 1.2 125 CURRENT LIMITED BY PACKAGE POWER DISSIPATION MULTIPLIER 1.0 100 0.8 ID, DRAIN CURRENT (A) 75 VGS = 10V 50 0.6 0.4 0.2 25 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175 Figure 1. Normalized Power Dissipation vs Ambient Temperature 2 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 Figure 2. Maximum Continuous Drain Current vs Case Temperature ZJC, NORMALIZED THERMAL IMPEDANCE PDM 0.1 t1 t2 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t , RECTANGULAR PULSE DURATION (s) 100 101 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC Figure 3. Normalized Maximum Transient Thermal Impedance 2000 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION TC = 25oC FOR TEMPERATURES ABOVE 25o C DERATE PEAK CURRENT AS FOLLOWS: 1000 IDM, PEAK CURRENT (A) VGS = 10V I = I25 175 - TC 150 100 50 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101 Figure 4. Peak Current Capability (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Typical Characteristics TA = 25C unless otherwise noted 400 10s 200 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] IAS, AVALANCHE CURRENT (A) 100 ID, DRAIN CURRENT (A) 100s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1ms 1 10ms SINGLE PULSE TJ = MAX RATED TC = 25o C 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200 DC 100 STARTING TJ = 25oC STARTING TJ = 150oC 10 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10 Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515 Figure 6. Unclamped Inductive Switching Capability 150 150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V ID, DRAIN CURRENT (A) VGS = 6V VGS = 10V 120 VGS = 5.5V 120 ID, DRAIN CURRENT (A) 90 TJ = 175o C 90 VGS = 5V 60 TC = 25o C PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 60 TJ = 25 oC 30 TJ = -55oC 30 0 3.0 3.5 4.0 4.5 5.0 5.5 VGS , GATE TO SOURCE VOLTAGE (V) 6.0 0 0 1 2 3 VDS , DRAIN TO SOURCE VOLTAGE (V) 4 Figure 7. Transfer Characteristics 10 DRAIN TO SOURCE ON RESISTANCE (m ) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = 6V Figure 8. Saturation Characteristics 2.5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.0 8 VGS = 10V 7 1.5 1.0 VGS = 10V, ID =80A 6 0 20 40 62 ID, DRAIN CURRENT (A) 80 0.5 -80 -40 0 40 80 120 TJ, JUNCTION TEMPERATURE (oC) 160 200 Figure 9. Drain to Source On Resistance vs Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Typical Characteristics TA = 25C unless otherwise noted 1.4 VGS = VDS, ID = 250A 1.2 NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.2 ID = 250A 1.0 1.1 0.8 0.6 1.0 0.4 0.2 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 0.9 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) 200 Figure 11. Normalized Gate Threshold Voltage vs Junction Temperature 10000 Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10 VDD = 50V VGS , GATE TO SOURCE VOLTAGE (V) C ISS = CGS + C GD C, CAPACITANCE (pF) COSS CDS + CGD 8 6 1000 CRSS = CGD 4 2 VGS = 0V, f = 1MHz 100 0.1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 100 WAVEFORMS IN DESCENDING ORDER: ID = 80A ID = 40A 0 20 40 60 Qg, GATE CHARGE (nC) 80 100 0 Figure 13. Capacitance vs Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Currents (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Test Circuits and Waveforms VDS tP L IAS VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP 0V RG VDD + BVDSS VDS VDD IAS 0.01 0 tAV Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS VDD Qg(TOT) VDS L VGS = 10V VGS + VDD DUT Ig(REF) 0 Qg(TH) VGS VGS = 2V Qgs2 Qgs Ig(REF) 0 Qgd Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS tON td(ON) RL VDS 90% tr tOFF td(OFF) tf 90% VGS + VDD DUT 0 10% 10% 90% VGS 50% PULSE WIDTH 50% RGS VGS 0 10% Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM , and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. (T -T ) JM A P D M = ----------------------------R JA 80 RJA = 26.51+ 19.84/(0.262+Area) EQ.2 RJA = 26.51+ 128/(1.69+Area) EQ.3 60 RJA (o C/W) 40 20 0.1 (0.645) 1 (6.45) AREA, TOP COPPER AREA in2 (cm2 ) 10 (64.5) (EQ. 1) In using surface mount devices such as the TO-263 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of P DM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Fairchild provides thermal information to assist the designer's preliminary application evaluation. Figure 21 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Fairchild device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeters square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. R JA Figure 21. Thermal Resistance vs Mounting Pad Area = 26.51 + ------------------------------------ 19.84 ( 0.262 + Area ) (EQ. 2) Area in Inches Squared R JA = 26.51 + --------------------------------- 128 ( 1.69 + Area ) (EQ. 3) Area in Centimeters Squared (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 PSPICE Electrical Model .SUBCKT FDB3632 2 1 3 ; CA 12 8 1.7e-9 Cb 15 14 2.5e-9 Cin 6 8 6.0e-9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 102.5 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5.61e-9 Ldrain 2 5 1.0e-9 Lsource 3 7 2.7e-9 RLgate 1 9 56.1 RLdrain 2 5 10 RLsource 3 7 27 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 3.8e-3 Rgate 9 20 1.1 RSLC1 5 51 RSLCMOD 1.0e-6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 2.5e-3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*350),3))} .MODEL DbodyMOD D (IS=5.9E-11 N=1.07 RS=2.3e-3 TRS1=3.0e-3 TRS2=1.0e-6 + CJO=4e-9 M=0.58 TT=4.8e-8 XTI=4.2) .MODEL DbreakMOD D (RS=0.17 TRS1=3.0e-3 TRS2=-8.9e-6) .MODEL DplcapMOD D (CJO=15e-10 IS=1.0e-30 N=10 M=0.6) .MODEL MstroMOD NMOS (VTO=4.1 KP=200 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL MmedMOD NMOS (VTO=3.4 KP=10.0 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1) .MODEL MweakMOD NMOS (VTO=2.75 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=1.1e+1 RS=0.1) .MODEL RbreakMOD RES (TC1=1.0e-3 TC2=-1.7e-6) .MODEL RdrainMOD RES (TC1=8.5e-3 TC2=2.8e-5) .MODEL RSLCMOD RES (TC1=2.0e-3 TC2=2.0e-6) .MODEL RsourceMOD RES (TC1=4e-3 TC2=1e-6) .MODEL RvthresMOD RES (TC1=-4.0e-3 TC2=-1.8e-5) .MODEL RvtempMOD RES (TC1=-4.4e-3 TC2=2.2e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-2) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-4) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.8 VOFF=0.4) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.4 VOFF=-0.8) .ENDS Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. GATE 1 RLGATE CIN rev May 2002 LDRAIN DPLCAP 10 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 MSTRO LSOURCE 8 RSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 7 RLSOURCE SOURCE 3 21 16 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED 5 DRAIN 2 RSLC2 5 51 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 - (c)2003 Fairchild Semiconductor Corporation + DBODY FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 SABER Electrical Model REV May 2002 template FDB3632 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=5.9e-11,nl=1.07,rs=2.3e-3,trs1=3.0e-3,trs2=1.0e-6,cjo=4e-9,m=0.58,tt=4.8e-8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e-3,trs2=-8.9e-6) dp..model dplcapmod = (cjo=15e-10,isl=10.0e-30,nl=10,m=0.6) m..model mstrongmod = (type=_n,vto=4.1,kp=200,is=1e-30, tox=1) m..model mmedmod = (type=_n,vto=3.4,kp=10.0,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=2.75,kp=0.05,is=1e-30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-2) LDRAIN sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-2,voff=-4) DPLCAP 5 DRAIN 2 sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.8,voff=0.4) 10 sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.4,voff=-0.8) RLDRAIN RSLC1 c.ca n12 n8 = 1.7e-9 51 c.cb n15 n14 = 2.5e-9 RSLC2 c.cin n6 n8 = 6.0e-9 ISCL dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 102.5 spe.eds n14 n8 n5 n8 = 1 GATE spe.egs n13 n8 n6 n8 = 1 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 5.61e-9 l.ldrain n2 n5 = 1.0e-9 l.lsource n3 n7 = 2.7e-9 res.rlgate n1 n9 = 56.1 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 27 CA LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8 50 RDRAIN 21 16 DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18 - RLGATE CIN MSTRO 8 LSOURCE 7 RLSOURCE SOURCE 3 RSOURCE S1A 12 S1B 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 RVTHRES 14 IT 15 17 RBREAK 18 RVTEMP 19 VBAT + 22 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.0e-3,tc2=-1.7e-6 res.rdrain n50 n16 = 3.8e-3, tc1=8.5e-3,tc2=2.8e-5 res.rgate n9 n20 = 1.1 res.rslc1 n5 n51 = 1.0e-6, tc1=2.0e-3,tc2=2.0e-6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 2.5e-3, tc1=4e-3,tc2=1e-6 res.rvthres n22 n8 = 1, tc1=-4.0e-3,tc2=-1.8e-5 res.rvtemp n18 n19 = 1, tc1=-4.4e-3,tc2=2.2e-6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/350))** 3)) } } (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. B1 FDB3632 / FDP3632 / FDI3632 SPICE Thermal Model REV May 2002 FDB3632 CTHERM1 TH 6 7.5e-3 CTHERM2 6 5 8.0e-3 CTHERM3 5 4 9.0e-3 CTHERM4 4 3 2.4e-2 CTHERM5 3 2 3.4e-2 CTHERM6 2 TL 6.5e-2 RTHERM1 TH 6 3.1e-4 RTHERM2 6 5 2.5e-3 RTHERM3 5 4 2.2e-2 RTHERM4 4 3 8.1e-2 RTHERM5 3 2 1.35e-1 RTHERM6 2 TL 1.5e-1 th JUNCTION RTHERM1 CTHERM1 6 RTHERM2 CTHERM2 5 SABER Thermal Model SABER thermal model FDB3632 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e-3 ctherm.ctherm2 6 5 =8.0e-3 ctherm.ctherm3 5 4 =9.0e-3 ctherm.ctherm4 4 3 =2.4e-2 ctherm.ctherm5 3 2 =3.4e-2 ctherm.ctherm6 2 tl =6.5e-2 rtherm.rtherm1 th 6 =3.1e-4 rtherm.rtherm2 6 5 =2.5e-3 rtherm.rtherm3 5 4 =2.2e-2 rtherm.rtherm4 4 3 =8.1e-2 rtherm.rtherm5 3 2 =1.35e-1 rtherm.rtherm6 2 tl =1.5e-1 } RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl CASE (c)2003 Fairchild Semiconductor Corporation FDB3632 / FDP3632 / FDI3632 Rev. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Preliminary No Identification Needed Full Production Obsolete Not In Production Rev. I2