DM54161 DM74161 DM74163 Synchronous 4-Bit Counters October 1992 DM54161 DM74161 DM74163 Synchronous 4-Bit Counters General Description These synchronous presettable counters feature an internal carry look-ahead for application in high-speed counting designs The 161 and 163 are 4-bit binary counters The carry output is decoded by means of a NOR gate thus preventing spikes during the normal counting mode of operation Synchronous operation is provided by having all flipflops clocked simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform These counters are fully programmable that is the outputs may be preset to either level As presetting is synchronous setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input The clear function for the 161 is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock load or enable inputs The clear function for the 163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse regardless of the levels of the enable inputs This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate The gate output is connected to the clear input to synchronously clear the counter to all low outputs Low-to-high transitions at the clear input of the 163 are also permissible regardless of the logic levels on the clock enable or load inputs The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output Both countenable inputs (P and T) must be high to count and input T is fed forward to enable the ripple carry output The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output This high-level overflow ripple carry pulse can be used to enable successive cascaded stages Highto-low-level transitions at the enable P or T inputs of the 161 through 163 may occur regardless of the logic level on the clock Features Y Y Y Y Y Y Synchronously programmable Internal look-ahead for fast counting Carry output for n-bit cascading Synchronous counting Load control line Diode-clamped inputs Connection Diagram Dual-In-Line Package TL F 6551 - 1 Order Number DM54161J DM54161W DM74161N or DM74163N See NS Package Number J16A N16E or W16A C1995 National Semiconductor Corporation TL F 6551 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range b 55 C to a 125 C DM54 DM74 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings The ``Recommended Operating Conditions'' table will define the conditions for actual device operation Recommended Operating Conditions Symbol VCC VIH VIL IOH IOL fCLK tW Parameter Min Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 6) Pulse Width (Note 6) Setup Time (Note 6) Clock Clear Data Enable P Load Clear (Note 5) tH TA Hold Time (Note 6) Free Air Operating Temperature 0 25 20 20 34 25 20 0 b 55 DM54161 Nom 5 Max 55 DM74161 and 163 Min 4 75 2 08 b0 8 Units V V Nom 5 Max 5 25 45 2 08 b0 8 V mA mA MHz ns 16 25 0 25 20 20 34 25 20 0 125 0 16 25 tSU ns ns 70 C Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH Parameter Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current Input Voltage Max Conditions VCC e Min II e b12 mA VCC e Min IOH e Max VIL e Max VIH e Min VCC e Min IOL e Max VIH e Min VIL e Max VCC e Max VI e 5 5V VCC e Max VI e 2 4V Enable T Clock Others IIL Low Level Input Current VCC e Max VI e 0 4V Enable T Clock Others 24 34 02 04 1 80 80 40 b3 2 b3 2 b1 6 Min Typ (Note 1) Max b1 5 Units V V V mA High Level Input Current mA mA 2 Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted) (Continued) Symbol IOS Parameter Short Circuit Output Current Supply Current with Outputs High Supply Current with Outputs Low Conditions VCC e Max (Note 2) VCC e Max (Note 3) VCC e Max (Note 4) DM54 DM74 DM54 DM74 DM54 DM74 63 59 Min b 20 b 20 Typ (Note 1) Max b 57 b 57 Units mA ICCH 85 94 91 101 mA ICCL mA Note 1 All typicals are at VCC e 5V TA e 25 C Note 2 Not more than one output should be shorted at a time Note 3 ICCH is measured with the LOAD high then again with the LOAD low with all inputs high and all outputs open Note 4 ICCL is measured with the CLOCK high then again with the CLOCK input low with all inputs low and all outputs open Note 5 Applies to 163 which has synchronous clear inputs Note 6 TA e 25 C and VCC e 5V Switching Characteristics at VCC e 5V and TA e 25 C (See Section 1 for Test Waveforms and Output Load) Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output Clock to Ripple Carry Clock to Ripple Carry Clock (Load High) to Q Clock (Load High) to Q Clock (Load Low) to Q Clock (Load Low) to Q Enable T to Ripple Carry Enable T to Ripple Carry Clear (Note 7) to Q From (Input) To (Output) RL e 400X CL e 15 pF Min 25 35 35 20 23 25 29 16 16 38 Max MHz ns ns ns ns ns ns ns ns ns Units Note 7 Propagation delay for clearing is measured from the clear input for the 161 or from the clock input transition for the 163 3 Logic Diagrams 161 TL F 6551 - 3 4 Logic Diagrams (Continued) 163 TL F 6551 - 8 5 Logic Diagrams (Continued) 161 163 Synchronous Binary Counters Typical Clear Preset Count and Inhibit Sequences TL F 6551 - 5 (1) (2) (3) (4) Clear outputs to zero Reset to binary twelve Count to thirteen fourteen fifteen zero one and two Inhibit 6 Parameter Measurement Information Switching Time Waveforms TL F 6551 - 6 Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT tr s 10 ns tf s 10 ns Vary PRR to measure fMAX Note B Outputs QD and carry are tested at tn a 16 for 161 163 where tn is the bit time when all outputs are low Note C For 161 and 163 VREF e 1 5V 50X For 161 and 163 7 Parameter Measurement Information (Continued) Switching Time Waveforms TL F 6551 - 7 Note A The input pulses are supplied by generators having the following characteristics PRR s 1 MHz duty cycle s 50% ZOUT tr s 10 ns tf s 10 ns Vary PRR to measure fMAX Note B Enable P and enable T setup times are measured at tn a 0 Note C For 161 and 163 VREF e 1 5V 50X For 161 and 163 8 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54161J or DM54163AJ NS Package Number J16A 16-Lead Molded Dual-In-Line Package (N) Order Number DM74161N or DM74163N NS Package Number N16E 9 DM54161 DM74161 DM74163 Synchronous 4-Bit Counters Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number DM54161W or DM54163AW NS Package Number W16A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications