Delta39KTM ISRTM CPLD Family CPLDs at FPGA DensitiesTM Features * High density -- 30K to 200K usable gates -- 512 to 3072 macrocells -- 136 to 428 maximum I/O pins -- Twelve dedicated inputs including four clock pins, four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfigurability Embedded memory -- 80K to 480K bits embedded SRAM * 16K to 96K bits of (dual-port) channel memory High speed - 233-MHz in-system operation AnyVoltTM interface -- 3.3V, 2.5V,1.8V, and 1.5V I/O capability Low-power operation -- 0.18-mm six-layer metal SRAM-based logic process -- Full-CMOS implementation of product term array -- Standby current as low as 5mA * Simple timing model -- No penalty for using full 16 product terms/macrocell -- No delay for single product term steering or sharing * Flexible clocking -- Spread AwareTM PLL drives all four clock networks * Allows 0.6% spread spectrum input clocks * Several multiply, divide and phase shift options -- Four synchronous clock networks per device -- Locally generated product term clock -- Clock polarity control at each register * Carry-chain logic for fast and efficient arithmetic operations * Multiple I/O standards supported -- LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ * Compatible with NOBLTM, ZBTTM, and QDRTM SRAMs * Programmable slew rate control on each I/O pin * User-programmable Bus Hold capability on each I/O pin * Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec, rev. 2.2) * CompactPCI hot swap ready * Multiple package/pinout offering across all densities -- 208 to 676 pins in PQFP, BGA, and FBGA packages -- Simplifies design migration across density -- Self-BootTM solution in BGA and FBGA packages * In-System ReprogrammableTM (ISRTM) -- JTAG-compliant on-board programming -- Design changes do not cause pinout changes * IEEE1149.1 JTAG boundary scan * * * * Development Software * Warp(R) -- IEEE 1076/1164 VHDL or IEEE 1364 Verilog context sensitive editing -- Active-HDL FSM graphical finite state machine editor -- Active-HDL SIM post-synthesis timing simulator -- Architecture Explorer for detailed design analysis -- Static Timing Analyzer for critical path analysis -- Available on Windows 95/98/2000/XPTM and Windows NTTM for $99 -- Supports all Cypress programmable logic products Delta39KTM ISR CPLD Family Members Typical Gates[1] 16K - 48K 23K - 72K 46K - 144K 77K - 241K 92K - 288K Cluster memory (Kbits) 64 96 192 320 384 Channel memory (Kbits) 16 24 48 80 96 Maximum I/O Pins 174 218 302 386 428 fMAX2 (MHz) 233 233 222 181 181 Speed-tPD Pin-to-Pin (ns) 7.2 7.2 7.5 8.5 8.5 Standby ICC[2] TA = 25C 3.3/2.5V 5 mA 5 mA 10 mA 20 mA 20 mA Device 39K30 39K50 39K100 39K165 39K200 Macrocells 512 768 1536 2560 3072 Notes: 1. Upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. Standby ICC values are with PLL not utilized, no output load and stable inputs. Cypress Semiconductor Corporation Document #: 38-03039 Rev. *H * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised August 1, 2003 Delta39KTM ISRTM CPLD Family Delta39K Speed Bins[3] Device 39K30 39K50 39K100 39K165 39K200 VCC 3.3/2.5V 3.3/2.5V 3.3/2.5V 3.3/2.5V 3.3/2.5V 233 X X X X X 200 181 125 X X X X X 83 X X X X X Device Package Offering and I/O Count Including Dedicated Clock and Control Inputs Self-Boot Solution[4] 208 EQFP 28 x 28 mm 0.5-mm pitch 136 136 136 136 136 256 FBGA 17 x 17 mm 1.0-mm pitch 174 180 180 302 356 368 484-FBGA 23 x 23 mm 1.0-mm pitch 256-FBGA 17 x 17 mm 1.0-mm pitch 174 218 294 294 294 218 302 386 428 388-BGA 35 x 35 mm 1.27-mm pitch 484-FBGA 23 x 23 mm 1.0-mm pitch 676-FBGA 27 x 27 mm 1.0-mm pitch Device 39K30 39K50 39K100 39K165 39K200 Notes: 3. Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 38. 4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000 programming/erase cycles and can retain data for at least 100 years. Document #: 38-03039 Rev. *H Page 2 of 86 Delta39KTM ISRTM CPLD Family GCLK[3:0] PLL and Clock MUX GCTL[3:0] 4 4 GCLK[3:0] 4 I/O Bank 7 4 4 I/O Bank 6 4 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[3:0] 4 4 4 4 I/O Bank 0 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM GCLK[3:0] 4 4 4 4 I/O Bank 1 LB 0 LB 1 LB 2 LB 3 Cluster RAM LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 LB 0 LB 1 LB 7 LB 6 PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM LB 2 LB 3 Cluster RAM PIM LB 5 LB 4 Cluster RAM Channel RAM I/O Bank 2 I/O Bank 3 Figure 1. Delta39K100 Block Diagram (Three Rows x Four Columns) with I/O Bank Structure General Description The Delta39K family, based on a 0.18-mm, six-layer metal CMOS logic process, offers a wide range of high-density solutions at unparalleled system performance. The Delta39K family is designed to combine the high speed, predictable timing, and ease of use of CPLDs with the high densities and low power of FPGAs. With devices ranging from 30,000 to 200,000 usable gates, the family features devices ten times the size of previously available CPLDs. Even at these large densities, the Delta39K family is fast enough to implement a fully synthesizable 64-bit, 66-MHz PCI core. Document #: 38-03039 Rev. *H The architecture is based on Logic Block Clusters (LBC) that are connected by Horizontal and Vertical (H and V) routing channels. Each LBC features eight individual Logic Blocks (LB) and two cluster memory blocks. Adjacent to each LBC is a channel memory block, which can be accessed directly from the I/O pins. Both types of memory blocks are highly configurable and can be cascaded in width and depth. See Figure 1 for a block diagram of the Delta39K architecture. All the members of the Delta39K family have Cypress's highly regarded In-System Reprogrammability (ISR) feature, which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconPage 3 of 86 I/O Bank 4 I/O Bank 5 Delta39KTM ISRTM CPLD Family figure the devices without having design changes cause pinout or timing changes in most cases. The Cypress ISR function is implemented through a JTAG-compliant serial interface. Data is shifted in and out through the TDI and TDO pins respectively. Superior routability, simple timing, and the ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance. The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Delta39K family also features user programmable bus-hold and slew rate control capabilities on each I/O pin. AnyVolt Interface All Delta39KV devices feature an on-chip regulator, which accepts 3.3V or 2.5V on the VCC supply pins and steps it down to 1.8V internally, the voltage level at which the core operates. With Delta39K's AnyVolt technology, the I/O pins can be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices are 3.3V-tolerant regardless of VCCIO or VCC settings. Table 1. Device 39KV VCC 3.3V or 2.5V VCCIO 3.3V or 2.5V or 1.8V or 1.5V[5] Global Routing Description The routing architecture of the Delta39K is made up of horizontal and vertical (H and V) routing channels. These routing channels allow signals from each of the Delta39K architectural components to communicate with one another. In addition to the horizontal and vertical routing channels that interconnect the I/O banks, channel memory blocks, and logic block clusters, each LBC contains a Programmable Interconnect Matrix (PIMTM), which is used to route signals among the logic blocks and the cluster memory blocks. Figure 2 is a block diagram of the routing channels that interface within the Delta39K architecture. The LBC is exactly the same for every member of the Delta39K CPLD family. Logic Block Cluster (LBC) The Delta39K architecture consists of several logic block clusters, each of which have eight Logic Blocks (LB) and two cluster memory blocks connected via a Programmable Interconnect Matrix (PIM) as shown in Figure 3. Each cluster memory block consists of 8-Kbit single-port RAM, which is configurable as synchronous or asynchronous. The cluster memory blocks can be cascaded with other cluster memory blocks within the same LBC as well as other LBCs to implement larger memory functions. If a cluster memory block is not specifically utilized by the designer, Cypress's Warp software can automatically use it to implement large blocks of logic. All LBCs interface with each other via horizontal and vertical routing channels. I/O Block LB LB LB LB Cluster Memory Block LB 72 LB Cluster PIM 64 LB LB Cluster Memory Block Channel Memory Block Channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels 72 I/O Block 64 H-to-V PIM V-to-H PIM Pin inputs from the I/O cells drive dedicated tracks in the horizontal and vertical routing channels Figure 2. Delta39K Routing Interface Note: 5. For HSTL only. Document #: 38-03039 Rev. *H Page 4 of 86 Delta39KTM ISRTM CPLD Family Clock Inputs GCLK[3:0] 4 Logic Block 0 CC 36 16 36 16 Logic Block 7 CC Logic Block 1 CC 36 16 36 16 Logic Block 6 CC Logic Block 2 CC 36 16 PIM 36 16 Logic Block 5 CC Logic Block 3 36 16 36 16 Logic Block 4 Cluster Memory 0 25 8 25 8 Cluster Memory 1 CC = Carry Chain 64 Inputs From Horizontal Routing Channel 64 Inputs From Vertical Routing Channel 144 Outputs to Horizontal and Vertical cluster-to-channel PIMs Figure 3. Delta39K Logic Block Cluster Diagram Logic Block The LB is the basic building block of the Delta39K architecture. It consists of a product term array, an intelligent product-term allocator, and 16 macrocells. Product Term Array Each logic block features a 72 x 83 programmable product term array. This array accepts 36 inputs from the PIM. These inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 83 product terms in the array can be created from any of the 72 inputs. Of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. The final product term is the Product Term clock (PTCLK) and is shared by all 16 macrocells within a logic block. Product Term Allocator Through the product term allocator, Warp software automatically distributes the 80 product terms as needed among the 16 macrocells in the logic block. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing. Product Term Steering Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will "steer" ten product terms to one macrocell and three to the other. On Delta39K devices, product terms are steered on an individual basis. Any number between 1 and 16 product terms can be steered to any macrocell. Product Term Sharing Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only programmed once. The Delta39K product term allocator allows sharing across groups of four macrocells in a variable fashion. The software automatically takes advantage of this capability so that the user does not have to intervene. Note that neither product term sharing nor product term steering have any effect on the speed of the product. All steering and sharing configurations have been incorporated in the timing specifications for the Delta39K devices. . Document #: 38-03039 Rev. *H Page 5 of 86 Delta39KTM ISRTM CPLD Family Macrocell Within each logic block there are 16 macrocells. Each macrocell accepts a sum of up to 16 product terms from the product term array. The sum of these 16 product terms can be output in either registered or combinatorial mode. Figure 4 displays the block diagram of the macrocell. The register can be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be preset or reset based on an AND expression or an OR expression. An XOR gate in the Delta39K macrocell allows for many different types of equations to be realized. It can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the D flip-flop into a T flip-flop. The carry-chain input mux allows additional flexibility for the implementation of different types of logic. The macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even generic XOR logic. The output of the macrocell is either registered or combinatorial. Carry Chain Logic The Delta39K macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic operations. The carry logic connects macrocells in up to four logic blocks for a total of 64 macrocells. Effective data path operaCarry In (from macrocell n-1) 0 1 C tions are implemented through the use of carry-in arithmetic, which drives through the circuit quickly. Figure 4 shows that the carry chain logic within the macrocell consists of two product terms (CPT0 and CPT1) from the PTA and an input carry-in for carry logic. The inputs to the carry chain mux are connected directly to the product terms in the PTA. The output of the carry chain mux generates the carry-out for the next macrocell in the logic block as well as the local carry input that is connected to an input of the XOR input mux. Carry-in and a configuration bit are inputs to an AND gate. This AND gate provides a method of segmenting the carry chain in any macrocell in the logic block. Macrocell Clocks Clocking of the register is highly flexible. Four global synchronous clocks (GCLK[3:0]) and a PTCLK are available at each macrocell register. Furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell diagram in Figure 4). PRESET/RESET Configurations The macrocell register can be asynchronously preset and reset using the PRESET and RESET mux. Both signals are active high and can be controlled by either of two Preset/Reset product terms (PRC[1:0] in Figure 4) or GND. In situations where the PRESET and RESET are active at the same time, RESET takes priority over PRESET. PRESET Mux Carry Chain Mux CPT0 CPT1 C XOR Input Mux 3 C Output Mux 2 C PSET To PIM FROM PTM Up To 16 PTs Clock Mux GCLK[3:0] PTCLK 3 C PRC[1:0] 0 1 D Clock Polarity Mux Q C RES Q C Carry Out (to macrocell n+1) 3 C RESET Mux Figure 4. Delta39K Macrocell Document #: 38-03039 Rev. *H Page 6 of 86 Delta39KTM ISRTM CPLD Family Embedded Memory Each member of the Delta39K family contains two types of embedded memory blocks. The channel memory block is placed at the intersection of horizontal and vertical routing channels. Each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous Dual-Port RAM, Single-Port RAM, Read-Only memory (ROM), or synchronous FIFO memory. The memory organization is configurable as 4K x 1, 2K x 2, 1K x 4 and 512K x 8. The second type of memory block is located within each LBC and is referred to as a cluster memory block. Each LBC contains two cluster memory blocks that are 8192 bits in size. Similar to the channel memory blocks, the cluster memory blocks can be configured as 8K x 1, 4K x 2, 2K x 4 and 1K x 8 asynchronous or synchronous Single-Port RAM or ROM. Cluster Memory Each logic block cluster of the Delta39K contains two 8192-bit cluster memory blocks. Figure 5 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster PIM. The output of the cluster memory block can be optionally registered to perform synchronous pipelining or to register asynchronous Read and Write operations. The output registers contain an asynchronous RESET which can be used in any type of sequential logic circuits (e.g., state machines). There are four global clocks (GCLK[3:0]) and one local clock available for the input and the output registers. The local clock for the input registers is independent of the one used for the output registers. The local clock is generated in the user design in a macrocell or comes from an I/O pin. Cluster Memory Initialization The cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use of look-up-table (LUT) logic and ROM applications, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory The Delta39K architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. The channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous single-port RAM, dual-port RAM, ROM, or synchronous FIFO memory. Data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. All data and FIFO logic outputs drive dedicated tracks in the horizontal and vertical routing channels. The clocks for the channel memory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. The clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. Dual-Port (Channel Memory) Configuration Each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. The inputs to the Dual-Port memory are driven from the horizontal and vertical routing channels. The data outputs drive dedicated tracks in the routing channels. The interface to the routing is such that Port A of the Dual-Port interfaces primarily with the horizontal routing channel and Port B interfaces primarily with the vertical routing channel. DIN[7:0] D Q C 3 Write Control Logic 2 C 8 ADDR[12:0] D Q C Row Decode (1024 Rows) WE D Q Write Pulse C 10 Cluster PIM GCLK[3:0] Local CLK 5:1 3 C DOUT[7:0] QD C R C 1024x8 Asynchronous SRAM 3 8 Read Control Logic 2 C RESET GCLK[3:0] Local CLK 5:1 3 C C Figure 5. Block Diagram of Cluster Memory Block Document #: 38-03039 Rev. *H Page 7 of 86 Delta39KTM ISRTM CPLD Family The clocks for each port of the Dual-Port configuration are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs of the dualport memory can also be registered. Clocks for the output registers are also selected from four global clocks and two local clocks. One clock polarity mux per port allows the use of true or complement polarity for input and output clocking purposes. Arbitration The Dual-Port configuration of the Channel Memory Block provides arbitration when both ports access the same address at the same time. Depending on the memory operation being attempted, one port always gets priority. See Table 2 for details on which port gets priority for Read and Write operations. An active-LOW "Address Match" signal is generated when an address collision occurs. Table 2. Arbitration Result: Address Match Signal Becomes Active Port A Port B Read Write Read Read Result of Arbitration No arbitration required Port A gets priority Comment Both ports read at the same time If Port B requests first then it will read the current data. The output will then change to the newly written data by Port A If Port A requests first then it will read the current data. The output will then change to the newly written data by Port B Port B is blocked until Port A is finished writing The FIFO block contains all of the necessary FIFO flag logic, including the Read and Write address pointers. The FIFO flags include an empty/full flag (EF), half-full flag (HF), and programmable almost-empty/full (PAEF) flag output. The FIFO configuration has the ability to perform simultaneous Read and Write operations using two separate clocks. These clocks may be tied together for a single operation or may run independently for asynchronous Read/Write (with regard to each other) applications. The data and control inputs to the FIFO block are driven from the horizontal or vertical routing channels. The data and flag outputs are driven onto dedicated routing tracks in both the horizontal and vertical routing channels. This allows the FIFO blocks to be expanded by using multiple FIFO blocks on the same horizontal or vertical routing channel without any speed penalty. In FIFO mode, the Write and Read ports are controlled by separate clock and enable signals. The clocks for each port are selected from four global clocks and two local clocks. One local clock is sourced from the horizontal channel and the other from the vertical channel. The data outputs from the Read port of the FIFO can also be registered. One clock polarity mux per port allows using true or complement polarity for Read and Write operations. The Write operation is controlled by the clock and the Write enable pin. The Read operation is controlled by the clock and the Read enable pin. The enable pins can be sourced from horizontal or vertical channels. Channel Memory Initialization The channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. To facilitate the use of look-up-table (LUT) logic and ROM applications, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. For LUT and ROM applications, the user cannot write to memory blocks. Channel Memory Routing Interface Similar to LBC outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in Figure 6. This allows the channel memory blocks to be expanded easily. These dedicated lines can be routed to I/O pins as chip outputs or to other logic block clusters to be used in logic equations. Read Write Port B gets priority Write Write Port A gets priority FIFO (Channel Memory) Configuration The channel memory blocks are also configurable as synchronous FIFO RAM. In the FIFO mode of operation, the channel memory block supports all normal FIFO operations without the use of any general-purpose logic resources in the device. Document #: 38-03039 Rev. *H Page 8 of 86 Delta39KTM ISRTM CPLD Family All channel memory inputs are driven from the routing channels 4096-bit Dual-Port Array Configurable as Async/Sync Dual-Port or Sync FIFO Vertical Channel Configurable as 4K x 1, 2K x 2, 1K x 4, and 512 x 8 block sizes Global Clock Signals GCLK[3:0] All channel memory outputs drive dedicated tracks in the routing channels Horizontal Channel Figure 6. Block Diagram of Channel Memory Block I/O Banks The Delta39K interfaces the horizontal and vertical routing channels to the pins through I/O banks. There are eight I/O banks per device as shown in Figure 7, and all I/Os from an I/O bank are located in the same section of a package for PCB layout convenience. Delta39K devices support True Vertical MigrationTM (i.e., for each package type, Delta39K devices of different densities keep given pins in the same I/O banks). This allows for easy and simple implementation of multiple I/O standards during the design and prototyping phase, before a final density has been determined. Please refer to the application note titled "Family, Package and Density Migration in Delta 39K and Quantum38K CPLDs." Each I/O bank contains several I/O cells, and each I/O cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. Each I/O cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. Each I/O bank can use any supported I/O standard by supplying appropriate VREF and VCCIO voltages and configuring the I/O through the Warp software. All the VREF and VCCIO pins in an I/O bank must be connected to the same VREF and VCCIO voltage respectively. This requirement restricts the number of I/O standards supported by an I/O bank at any given time. The number of I/Os which can be used in each I/O bank depend on the type of I/O standards and the number of VCCIO and GND pins being used. This restriction is derived from the electromigration limit of the VCCIO and GND bussing on the chip. Please refer to the note on page 17 and the application note titled "Delta39K Family Device I/O Standards and Configurations" for details. I/O Cell Figure 8 is a block diagram of the Delta39K I/O cell. The I/O cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. The output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. The input of the device and the pin output can each be configured as registered or combinatorial; however, only one path can be configured as registered in a given design. The output enable in an I/O cell can be selected from one of the four global control signals or from one of two Output Control Channel (OCC) signals. The output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. The selection is done via a mux that includes VCC and GND as inputs. bank 7 bank 1 bank 0 bank 6 bank 4 bank 5 Page 9 of 86 Delta39K Delta39K bank 2 bank 3 Figure 7. Delta39K I/O Bank Block Diagram Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Registered OE Mux OE Mux D From Output PIM Input Mux 3 C RES Q C To Routing Channel Output Control Channel OCC Global Clock Signals Global I/O Control Signals Register Input Mux C C Output Mux Register Enable Mux Clock Polarity Mux C D E Q C RES Bus Hold I/O C 3 Clock Mux Slew Rate Control C 2 C C Register Reset Mux 3 C Figure 8. Block Diagram of I/O Cell I/O Signals There are four dedicated inputs (GCTL[3:0]) that are used as Global I/O Control Signals available to every I/O cell. These global I/O control signals may be used as output enables, register resets and register clock enables as shown in Figure 8. These global control signals, driven from four dedicated pins, can only be used as active-high signals and are available only to the I/O cells thereby implementing fast resets, register and output enables. In addition, there are six OCC signals available to each I/O cell. These control signals may be used as output enables, register resets and register clock enables as shown in Figure 8. Unlike global control signals, these OCC signal can be driven from internal logic or and I/O pin. One of the four global clocks can be selected as the clock for the I/O cell register. The clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock Slew Rate Control The output buffer has a slew rate control option. This allows the output buffer to slew at a fast rate (3 V/ns) or a slow rate (1 V/ns). All I/Os default to fast slew rate. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance. Table 3. I/O Standards I/O Standard LVTTL LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV 0.9 1.3 1.3 1.15 1.15 0.68 0.68 0.68 0.68 1.1 1.7 1.7 1.35 1.35 0.9 0.9 0.9 0.9 VREF (V) Min. N/A Max. 3.3V 3.3V 3.0V 2.5V 1.8V 3.3V N/A 3.3V 3.3V 2.5V 2.5V 1.5V 1.5V 1.5V 1.5V N/A N/A N/A N/A N/A N/A 1.5 1.5 1.5 1.25 1.25 0.75 0.75 1.5 1.5 VCCIO Termination Voltage (VTT) Document #: 38-03039 Rev. *H Page 10 of 86 Delta39KTM ISRTM CPLD Family Programmable Bus Hold On each I/O pin, user-programmable-bus-hold is included. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in businterface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note titled "Understanding Bus-Hold-A Feature of Cypress CPLDs." Clocks Delta39K has four dedicated clock input pins (GCLK[3:0]) to accept system clocks. One of these clocks (GCLK[0]) may be selected to drive an on-chip phase-locked loop (PLL) for frequency modulation (see Figure 9 for details). The global clock tree for a Delta39K device can be driven by a combination of the dedicated clock pins and/or the PLLderived clocks. The global clock tree consists of four global clocks that go to every macrocell, memory block, and I/O cell. Clock Tree Distribution The global clock tree performs two primary functions. First, the clock tree generates the four global clocks by multiplexing four dedicated clocks from the package pins and four PLL driven clocks. Second, the clock tree distributes the four global clocks to every cluster, channel memory, and I/O block on the die. The global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. Spread Aware PLL Each device in the Delta39K family features an on-chip PLL designed using Spread Aware technology for low EMI applications. In general, PLLs are used to implement time-divisionmultiplex circuits to achieve higher performance with fewer device resources. off-chip signal (external feedback) INTCLK0, INTCLK1, INTCLK2, INTCLK3 Any Register (TFF) Send a global clock off chip GCLK1 Normal I/O signal path Lock Detect/IO pin C For example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit circuitry that runs internally at 80 MHz. PLLs can also be used to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. There are several frequency multiply (X1, X2, X3, X4, X5, X6, X8, X16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (GCLK[0]). For increased flexibility, there are seven phase shifting options which allow clock skew/deskew by 45, 90, 135, 180, 225, 270, or 315. The Spread Aware feature refers to the ability of the PLL to track a spread-spectrum input clock such that its spread is seen on the output clock with the PLL staying locked. The total amount of spread on the input clock should be limited to 0.6% of the fundamental frequency. Spread Aware feature is supported only with X1, X2, and X4 multiply options. The Voltage Controlled Oscillator (VCO), the core of the Delta39K PLL is designed to operate within the frequency range of 100 MHz to 266 MHz. Hence, the multiply option combined with input (GCLK[0]) frequency should be selected such that this VCO operating frequency requirement is met. This is demonstrated in Table 4 (columns 1, 2, and 3). Another feature of this PLL is the ability to drive the output clock (INTCLK) off the Delta39K chip to clock other devices on the board, as shown in Figure 9 above. This off-chip clock is half the frequency of the output clock as it has to go through a register (I/O register or a macrocell register). This PLL can also be used for board de-skewing purpose by driving a PLL output clock off-chip, routing it to the other devices on the board and feeding it back to the PLL's external feedback input (GCLK[1]). When this feature is used, only limited multiply, divide and phase shift options can be used. Table 4 describes the valid multiply and divide options that can be used without external feedback. Table 5 describes the valid multiply and divide options that can be used with an external feedback. Clock Tree Delay Phase selection Divide 2 C 1-6,8,16 INTCLK0 GCLK0 fb fb Lock Phase selection Divide 1-6,8,16 Clk 00 0 Clk 45 INTCLK1 GCLK1 Phase selection Divide 1-6,8,16 INTCLK2 GCLK2 2 Phase selection Divide 1-6,8,16 INTCLK3 GCLK3 2 C 2 C 2 C GCLK0 Source Clock Clk 0 90 0 Clk 135 0 Clk 180 Clk 0 225 Clk 0 270 Clk PLL 0 315 X1, X2, X3, X4, 5X, X6, X8, X16 GCLK[3:0] C Figure 9. Block Diagram of Spread Aware PLL Page 11 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 6 describes the valid phase shift options that can be used with or without an external feedback. Table 7 is an example of the effect of all the available divide and phase shift options on a VCO output of 250 MHz. It also shows the effect of division on the duty cycle of the resultant clock. Note that the duty cycle is 50-50 when a VCO output is divided by an even number. Also note that the phase shift applies to the VCO output and not to the divided output. For more details on the architecture and operation of this PLL please refer to the application note entitled "Delta39K PLL and Clock Tree". Table 4. Valid PLL Multiply and Divide Options--without External Feedback Input Frequency (GCLK[0]) fPLLI (MHz) DC-12.5 100-133 50-133 33.3-88.7 25-66 20-53.2 16.6-44.3 12.5-33 12.5-16.625 Valid Multiply Options Value N/A 1 2 3 4 5 6 8 16 VCO Output Frequency (MHz) N/A 100-133 100-266 100-266 100-266 100-266 100-266 100-266 200-266 Value N/A 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 1-6, 8, 16 Valid Divide Options Output Frequency (INTCLK[3:0]) fPLLO (MHz) DC-12.5 6.25-133 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 6.25-266 Off-chip Clock Frequency DC-6.25 3.125-66 3.125-133 3.1-266 3.125-133 3.1-133 3.1-133 3.125-133 3.125-133 Table 5. Valid PLL Multiply and Divide Options--With External Feedback Valid Multiply Options Input (GCLK) Frequency fPLLI (MHz) 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Value 1 1 1 1 1 1 1 VCO Output Frequency (MHz) 100-266 100-266 100-266 100-266 125-266 150-266 200-266 Value 1 2 3 4 5 6 8 Valid Divide Options Output (INTCLK) Frequency fPLLO (MHz) 100-266 50-133 33.33-88.66 25-66.5 25-53.2 25-44.34 25-33.25 Off-chip Clock Frequency 50-133 25-66.5 16.67-44.33 12.5-33.25 12.5-26.6 12.5-22.17 12.5-16.63 Table 6. Recommended PLL Phase Shift Options Without External Feedback 0,45, 90, 135, 180, 225, 270, 315 0 With External Feedback Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz Divide Factor 1 2 3 4 5 6 8 16 Period (ns) 4 8 12 16 20 24 32 64 Duty Cycle% 40-60 50 33-67 50 40-60 50 50 50 0 (ns) 0 0 0 0 0 0 0 0 45 (ns) 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 90 (ns) 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 135 (ns) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 180 (ns) 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 225 (ns) 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 270 (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 315 (ns) 3.5 3.5 3.5 3.5 3.5 3.5 3.5 3.5 Document #: 38-03039 Rev. *H Page 12 of 86 Delta39KTM ISRTM CPLD Family CompactPCI Hot Swap The CompactPCI Hot Swap specification allows the removal and insertion of cards into CompactPCI sockets without switching-off the bus. Delta39K CPLDs can be used as a CompactPCI host or target on these cards. This feature is useful in telecommunication and networking applications as it allows implementation of high availability systems, where repairs and upgrades can be done without downtime. Delta39K CPLDs are CompactPCI Hot Swap Ready per CompactPCI Hot Swap specification R2.0, with the following exception: * The I/O cells do not provide bias voltage support. External resistors can be used to achieve this, per section 3.1.3.1 of the CompactPCI Hot Swap specification R2.0. A simple board level solution is provided in the application note titled "Hot-Swapping Delta39K and Quantum38K CPLDs." Timing Model One important feature of the Delta39K family is the simplicity of its timing. All combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the AC specs section) as long as data is routed through the same horizontal and vertical channels. Figure 10 illustrates the true timing model for the 200-MHz devices. For synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate Logic Blocks within the same cluster, as well as separate Logic Blocks within different clusters. This is respectively shown as tSCS and tSCS2 in Figure 10. For combinatorial paths, any input to any output (from corner to corner on the device), incurs a worstcase delay in the 39K100 regardless of the amount of logic or which horizontal and vertical channels are used. This is the tPD shown in Figure 10. For synchronous systems, the input setup time to the output macrocell register and the clock to output time are shown as the parameters tMCS and tMCCO shown in the Figure 10. These measurements are for any output and synchronous clock, regardless of the logic placement. The Delta39K features: * no dedicated vs. I/O pin delays * no penalty for using 0 - 16 product terms * no added delay for steering product terms * no added delay for sharing product terms * no output bypass delays. The simple timing model of the Delta39K family eliminates unexpected performance penalties. Family, Package, and Density Migration in Delta39K CPLDs The Delta39K CPLDs combine dense logic, embedded memory and configurable I/O standards. Further design flexibility is added by the easy migration options available between different packages and densities of Delta39K CPLD offerings. This migration flexibility makes changes or additions to designs simple even after PCB layout. It also provides the ability for experimental designs to be used on production PCBs. Please refer to the application note titled "Family, Package, and Density Migration in Delta39K CPLDs." Document #: 38-03039 Rev. *H Page 13 of 86 Delta39KTM ISRTM CPLD Family GCLK[3:0] 4 LB 0 LB 1 LB 7 LB 6 Channel RAM tSCS 4 LB 0 LB 1 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 8 Kb SRAM LB 4 8 Kb SRAM tMCS LB 3 Cluster RAM LB 4 Cluster RAM GCLK[3:0] 4 LB 0 LB 1 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM tSCS2 LB 2 PIM LB 5 LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM tPD LB 3 Cluster RAM LB 4 Cluster RAM GCLK[3:0] 4 LB 0 LB 1 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 0 LB 1 4 LB 7 LB 6 Channel RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM LB 2 PIM LB 5 LB 3 Cluster RAM LB 4 Cluster RAM tMCCO Figure 10. Timing Model for 39K100 Device IEEE 1149.1-compliant JTAG Operation The Delta39K family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR operations. Four dedicated pins are reserved on each device for use by the Test Access Port (TAP). Boundary Scan The Delta39K family supports Bypass, Sample/Preload, Extest, Intest, Idcode and Usercode boundary scan instructions. The JTAG interface is shown in Figure 11. In-System Reprogramming (ISR) In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Delta39K family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. Configuration Each device of the Delta39K family is available in a volatile and a Self-Boot package. Cypress's CPLD boot EEPROM is used to store configuration data for the volatile solution and an embedded on-chip FLASH memory device is used for the SelfBoot solution. For volatile Delta39K packages, programming is defined as the loading of a user's design into the external CPLD boot EEPROM. For Self-Boot Delta39K packages, programming is defined as the loading of a user's design into the on-chip FLASH internal to the Delta39K package. Configuration is defined as the loading of a user's design into the Delta39K die. Document #: 38-03039 Rev. *H Page 14 of 86 Delta39KTM ISRTM CPLD Family Instruction Register TDI TDO Bypass Reg. Boundary Scan idcode Usercode ISR Prog. Delta39K devices to complete the desired reconfiguration or diagnostic operations. Contact your local sales office for information on the availability of this option. Programming TMS TCLK JTAG TAP CONTROLLER The on-chip FLASH device of the Delta39K Self-Boot package is programmed by issuing the appropriate IEEE STD 1149.1 JTAG instruction to the internal FLASH memory via the JTAG interface. This can be done automatically using ISR/STAPL software. The configuration bits are sent from a PC through the JTAG port into the Delta39K via the C3ISR programming cable. The data is then internally passed from Delta39K to the on-chip FLASH. For more information on how to program the Delta39K through ISR/STAPL, please refer to the ISR/STAPL User Guide. The external CPLD boot EEPROM used to store configuration data for the Delta39K volatile package is programmed through Cypress's CYDH2200E CPLD Boot PROM Programming Kit via a two-wire interface. For more information on how to program the CPLD boot EEPROM, please refer to the data sheet titled "CYDH2200E CPLD Boot PROM Programming Kit." For more information on the architecture and timing specification of the boot EEPROM, refer to the data sheet titled "512K/1Mb CPLD Boot EEPROM" or "2-Mbit CPLD Boot EEPROM." Third-Party Programmers Cypress support is available on a wide variety of third-party programmers. All major programmers (including BP Micro, System General, Hi-Lo) support the Delta39K family. Data Registers Figure 11. JTAG Interface Configuration can begin in two ways. It can be initiated by toggling the Reconfig pin from LOW to HIGH, or by issuing the appropriate IEEE STD 1149.1 JTAG instruction to the Delta39K device via the JTAG interface. There are two IEEE STD 1149.1 JTAG instructions that initiate configuration of the Delta39K. The Self Config instruction causes the Delta39K to (re)configure with data stored in the serial boot PROM or the embedded FLASH memory. The Load Config instruction causes the Delta39K to (re)configure according to data provided by other sources such as a PC, automatic test equipment (ATE), or an embedded micro-controller/processor via the JTAG interface. For more information on configuring Delta39K devices, refer to the application note titled "Configuring Delta39K/Quantum38K" at http://www.cypress.com. There are two configuration options available for issuing the IEEE STD 1149.1 JTAG instructions to the Delta39K. The first method is to use a PC with the C3ISR programming cable and software. With this method, the ISR pins of the Delta39K devices in the system are routed to a connector at the edge of the printed circuit board. The C3ISR programming cable is then connected between the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on the Delta39K devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other ISR functions. For more information on the Cypress ISR interface, see the ISR Programming Kit data sheet (CY3900i). The second configuration option for the Delta39K is to utilize the embedded controller or processor that already exists in the system. The Delta39K ISR software assists in this method by converting the device HEX file into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be configured. The embedded controller then simply directs this ISR stream to the chain of Development Software Support Warp Warp is a state-of-the-art design environment for designing with Cypress programmable logic. Warp utilizes a subset of IEEE 1076/1164 VHDL and IEEE 1364 as the Hardware Description Language (HDL) for design entry. Warp accepts VHDL or Verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired Delta39K device. For simulation, Warp provides a graphical waveform simulator as well as VHDL and Verilog Timing Models. VHDL and Verilog are open, powerful, non-proprietary Hardware Description Languages (HDLs) that are standards for behavioral design entry and simulation. HDL allows designers to learn a single language that is useful for all facets of the design process. Third-Party Software Cypress products are supported in a number of third-party design entry and simulation tools. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third party vendors. Document #: 38-03039 Rev. *H Page 15 of 86 Delta39KTM ISRTM CPLD Family Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (39K200, 208 EQFP) ................................. -45C to +125C Storage Temperature (all other densities and packages) .............. -65C to +150C Soldering Temperature................................................. 220C Ambient Temperature with Power Applied............................................... -40C to +85C Junction Temperature...................................................135C VCC to Ground Potential...................................-0.5V to 4.6V VCCIO to Ground Potential................................-0.5V to 4.6V DC Voltage Applied to Outputs in High-Z state ..................................................-0.5V to 4.5V DC Input voltage...............................................-0.5V to 4.5V DC Current into Outputs........................................ 20 mA[6] Static Discharge Voltage (per JEDEC EIA./JESD22-A114A)............................ >2001V Latch-up Current ..................................................... >200 mA VCCJTAG/ VCCIO VCC VCCCNFG VCCPLL VCCPRG 3.3V 0.3V 3.3V 0.3V or Same as Same as 3.3V 2.5V 0.2V VCCIO VCC 0.3V 2.5V 0.2V (39KV) 1.8V 0.15V 1.5V 0.1V[5] 3.3V 0.3V 2.5V 0.2V 1.8V 0.15V 1.5V 0.1V[5] VCCIO = 3.3V VCCIO = 2.5V VCCIO = 1.8V Min. Max. Min. Max. Min. Max. 1.5 1.5 1.5 1.2 GND VI 3.6V GND VO VCCIO VCCIO = Max. VOUT = 0.5V VCC = Min. VPIN = VIL VCC = Min. VPIN = VIH VCC = Max. VCC = Max. 39K30 39K50 39K100 39K165 39K200 -10 -10 10 10 -160 +40 -40 +250 -250 All bins Operating Range Range Commercial Ambient Temperature 0C to +70C Junction Temperature 0C to +85C Output Condition 3.3V 2.5V 1.8V 1.5V 3.3V 2.5V 1.8V 1.5V Industrial -40C to +85C -40C to +100C DC Characteristics Parameter Description VDRINT Data Retention VCC Voltage (config data may be lost below this) VDRIO Data Retention VCCIO Voltage (config data may be lost below this) IIX[7] Input Leakage Current IOZ Output Leakage Current IOS[8] IBHL IBHH IBHLO IBHHO ICC0 Output Short Circuit Current Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current Standby Current Test Conditions Unit V V 10 10 -160 +25 -25 +200 -200 All bins 1.2 -10 -10 10 10 -160 +30 -30 1.2 -10 -10 A A A A A +150 -150 -125 bin -83 bin 20 20 30 60 60 20 20 30 60 60 3 3 5 10 10 12 12 20 40 40 A A A Note: 6. DC current into outputs is 36 mA with HSTL III, 48 mA with HSTL IV, and 36 mA with GTL+ (with 25W pull-up resistor and V TT = 1.5). 7. Input Leakage current is 10A for all the pins on all the Delta39K package except the following pins in Delta39K100 packages: The input leakage current spec for these pins in 200A Delta39K100 Package Pins 388-BGA B4, C2 484-FBGA B8, G9 676-FBGA F11, J11 8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester-ground degradation. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-03039 Rev. *H Page 16 of 86 Delta39KTM ISRTM CPLD Family Capacitance Parameter CI/O CCLK CPCI Description Input/Output Capacitance Clock Signal Capacitance PCI-compliant[9] Capacitance Test Conditions Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C Vin = VCCIO @ f = 1 MHz 25C Min. 5 Max. 10 12 8 Unit pF pF pF DC Characteristics (I/O)[10] VOH (V) VREF VCCIO I/O Standards (V) (V) LVTTL -2 mA LVTTL -4 mA LVTTL -6 mA LVTTL -8 mA LVTTL -12 mA LVTTL -16 mA LVTTL -24 mA LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV 1.0 1.5 1.5 1.25 1.25 0.75 0.75 0.9 0.9 1.8 3.3 [11] @ IOH = -2 mA -4 mA -6 mA -8 mA -12 mA -16 mA -24 mA -0.1 mA -0.1 mA -0.1 mA -1.0 mA -2.0 mA VOH (min.) 2.4 2.4 2.4 2.4 2.4 2.4 2.4 VCCIO - 0.2V VCCIO - 0.2V 2.1 2.0 1.7 VOL (V) VOL @ IOL = (max.) 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 0.1 mA 0.1 mA 0.1 mA 1.0 mA 2.0 mA 2.0 mA 1.5 mA 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.2 0.2 0.2 0.4 0.7 0.45 0.1VCCIO 0.6 0.7 0.5 0.54 0.35 0.4 0.4 0.4 0.4 VIH (V) Min. 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 2.0V 1.7V Max. Min. VIL (V) Max. 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.8V 0.7V N/A 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.0 2.5 VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V VCCIO + 0.3 -0.3V -2 mA VCCIO - 0.45V -0.5 mA 0.9VCCIO -8 mA 0.65VCCIO 0.5VCCIO VCCIO + 0.3 -0.3V VCCIO + 0.5 -0.5V 0.35VCCIO 0.3VCCIO 3.3 3.3 2.5 2.5 1.5 1.5 1.5 1.5 36 mA[12] VCCIO - 1.1V 8 mA 16 mA 7.6 mA VREF + 0.2 VREF - 0.2 VREF + 0.2 VCCIO + 0.3 -0.3V VREF - 0.2 VREF + 0.2 VCCIO + 0.3 -0.3V VREF - 0.2 VREF + 0.18 VCCIO + 0.3 -0.3V VREF - 0.18 VREF + 0.18 VCCIO + 0.3 -0.3V VREF - 0.18 VREF + 0.1 VCCIO + 0.3 -0.3V VREF - 0.1 VREF + 0.1 VCCIO + 0.3 -0.3V VREF - 0.1 VREF + 0.1 VCCIO + 0.3 -0.3V VREF - 0.1 VREF + 0.1 VCCIO + 0.3 -0.3V VREF - 0.1 -16 mA VCCIO - 0.9V -7.6 mA VCCIO - 0.62V -15.2 mA VCCIO - 0.43V 15.2 mA -8 mA VCCIO - 0.4V 8 mA -16 mA VCCIO - 0.4V 16 mA -8 mA VCCIO - 0.4V 24 mA -8 mA VCCIO - 0.4V 48 mA Configuration Parameters Parameter tRECONFIG Description Reconfig pin LOW time before it goes HIGH Min. 200 Unit ns Power-up Sequence Requirements * Upon power-up, all the outputs remain three-stated until all the VCC pins have powered-up to the nominal voltage and the part has completed configuration. * The part will not start configuration until VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG have reached nominal voltage. * VCC pins can be powered up in any order. This includes VCC, VCCIO, VCCJTAG, VCCCNFG, VCCPLL and VCCPRG. * All VCCIOs on a bank should be tied to the same potential and powered up together. * All VCCIOs (even the unused banks) need to be powered up to at least 1.5V before configuration has completed. * Maximum ramp time for all VCCs should be 0V to nominal voltage in 100 ms. Notes: 9. PCI spec (rev 2.2) requires the IDSEL pin to have capacitance less than or equal to 8 pF. Delta39K Pin Tables starting from page 45, identify all the I/O pins in a given package, which can be used as IDSEL in a PCI design. All other I/O pins meet the PCI requirement of capacitance less than or equal to 10 pf. 10. The number of I/Os which can be used in each I/O bank depends on the type of I/O standards and the number of VCCIO and GND pins being used. Please refer to the application note titled "Delta39K and Quantum38K I/O Standards and Configurations" for details. * The source current limit per I/O bank per Vccio pin is 165 mA. * The sink current limit per I/O bank per GND pin is 230 mA. 11. See "Power-up Sequence Requirements" below for VCCIO requirement. 12. 25W resistor terminated to termination voltage of 1.5V. Document #: 38-03039 Rev. *H Page 17 of 86 Delta39KTM ISRTM CPLD Family Switching Characteristics -- Parameter Descriptions Over the Operating Range[13] Parameter Combinatorial Mode Parameters tPD tEA tER tPRR tPRO tPRW Delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster Global control to output enable Global control to output disable Asynchronous macrocell RESET or PRESET recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with Set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock Global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in Set-up time of any input pin to the I/O cell register associated with that pin, relative to a global clock Hold time of any input pin to the I/O cell register associated with that pin, relative to a global clock Clock to output of an I/O cell register to the output pin associated with that register Macrocell clock to macrocell clock through array logic within the same cluster Macrocell clock to macrocell clock through array logic in different clusters on the same channel I/O register clock to any macrocell clock in a cluster on the channel the I/O register is associated with Macrocell clock to any I/O register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in Clock to output disable (high-impedance) Clock to output enable (low-impedance) Maximum frequency with internal feedback--within the same cluster Maximum frequency with internal feedback--within different clusters at the opposite ends of a horizontal or vertical channel Set-up time for macrocell used as input register, from input to product term clock Hold time of macrocell used as an input register Product term clock to output delay from input pin Register to register delay through array logic in different clusters on the same channel using a product term clock Adder for a signal to switch from a horizontal to vertical channel and vice-versa Cluster-to-cluster delay adder (through channels and channel PIM) Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster PIM input. This parameter can be added to the tPD and tSCS parameters for each extra pass through the AND/OR array required by a given signal path Adder for carry chain logic per macrocell Delay from the input of the output buffer to the I/O pin Delay from the I/O pin to the input of the channel buffer Description Synchronous Clocking Parameters tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2 tMCSPT tMCHPT tMCCOPT tSCS2PT tCHSW tCL2CL Product Term Clock Channel Interconnect Parameters Miscellaneous Delays tCPLD tMCCD tIOD tIOIN Note: 13. Add tCHSW to signals making a horizontal to vertical channel switch or vice-versa. Document #: 38-03039 Rev. *H Page 18 of 86 Delta39KTM ISRTM CPLD Family Switching Characteristics -- Parameter Descriptions Over the Operating Range[13] (continued) Parameter tCKIN tIOREGPIN tMCCJ tDWSA tDWOSA tLOCK tINDUTY fPLLI fPLLO fPLLVCO PSAPLLI fMPLLI Description Delay from the clock pin to the input of the clock driver Delay from the I/O pin to the input of the I/O register Maximum cycle to cycle jitter time PLL zero phase delay with clock tree deskewed PLL zero phase delay without clock tree deskewed Lock time for the PLL Input duty cycle Input frequency of the PLL Output frequency of the PLL PLL VCO frequency of operation Percentage modulation allowed (spread awareness) on the PLL input clock Frequency of modulation allowed on PLL input clock. This specifies how fast the fPLLI sweeps between fPLLI* (1-PSAPLLI/100) and fPLLI* (1+ PSAPLLI/100) TCLK HIGH time TCLK LOW time TCLK clock period JTAG port set-up time (TDI/TMS inputs) JTAG port hold time (TDI/TMS inputs) JTAG port clock to output time (TDO) JTAG port valid output to high impedance (TDO) JTAG port high impedance to valid output (TDO) PLL Parameters JTAG Parameters tJCKH tJCKL tJCP tJSU tJH tJCO tJXZ tJZX Cluster Memory Timing Parameter Descriptions Over the Operating Range Parameter Asynchronous Mode Parameters tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 Cluster memory access time. Delay from address change to Read data out Write Enable pulse width Address set-up to the beginning of Write Enable with both signals from the same I/O block Address hold after the end of Write Enable with both signals from the same I/O block Data set-up to the end of Write Enable Data hold after the end of Write Enable Clock cycle time for flow through Read and Write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) Clock cycle time for pipelined Read and Write operations (from cluster memory input register through the memory to cluster memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data Cluster memory input clock to macrocell clock in the same cluster Cluster memory output clock to macrocell clock in the same cluster Macrocell clock to cluster memory input clock in the same cluster Page 19 of 86 Description Synchronous Mode Parameters Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Cluster Memory Timing Parameter Descriptions Over the Operating Range (continued) Parameter tMACCLMS2 tCLMCLAA Internal Parameters Asynchronous cluster memory access time from input of cluster memory to output of cluster memory Description Macrocell clock to cluster memory output clock in the same cluster Channel Memory Timing Parameter Descriptions Over the Operating Range Parameter Dual Port Asynchronous Mode Parameters tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA Channel memory access time. Delay from address change to Read data out Write enable pulse width Address set-up to the beginning of Write enable with both signals from the same I/O block Address hold after the end of Write enable with both signals from the same I/O block Data set-up to the end of Write enable Data hold after the end of Write enable Channel memory asynchronous dual port address match (busy access time) Clock cycle time for flow through Read and Write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) Clock cycle time for pipelined Read and Write operations (from channel memory input register through the memory to channel memory output register) Address, data, and WE set-up time of pin inputs, relative to a global clock Address, data, and WE hold time of pin inputs, relative to a global clock Global clock to data valid on output pins for flow through data Global clock to data valid on output pins for pipelined data. Channel memory synchronous dual-port address match (busy, clock to data valid) Channel memory input clock to macrocell clock in the same cluster Channel memory output clock to macrocell clock in the same cluster Macrocell clock to channel memory input clock in the same cluster Macrocell clock to channel memory output clock in the same cluster Read and Write minimum clock cycle time Data, Read enable, and Write enable set-up time relative to pin inputs Data, Read enable, and Write enable hold time relative to pin inputs Data access time to output pins from rising edge of Read clock (Read clock to data valid) Channel memory FIFO Read clock to macrocell clock for Read data Macrocell clock to channel memory FIFO Write clock for Write data Read or Write clock to respective flag output at output pins Read or Write clock to macrocell clock with FIFO flag Master Reset Pulse Width Master Reset Recovery Time Master Reset to Flag and Data Output Time Read/Write Clock Skew Time for Full Flag Read/Write Clock Skew Time for Empty Flag Read/Write Clock Skew Time for Boundary Flags Description Dual Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 Synchronous FIFO Data Parameters Synchronous FIFO Flag Parameters Document #: 38-03039 Rev. *H Page 20 of 86 Delta39KTM ISRTM CPLD Family Channel Memory Timing Parameter Descriptions Over the Operating Range (continued) Parameter Internal Parameters tCHMCHAA Asynchronous channel memory access time from input of channel memory to output of channel memory Description Switching Characteristics -- Parameter Values Over the Operating Range 233 Parameter tPD tEA tER tPRR tPRO tPRW tMCS tMCH tMCCO tIOS tIOH tIOCO tSCS tSCS2 tICS tOCS tCHZ tCLZ fMAX fMAX2 tMCSPT tMCHPT tMCCOPT tSCS2PT tCHSW tCL2CL Miscellaneous Parameters tCPLD tMCCD PLL Parameters tMCCJ tDWSA tDWOSA tLOCK Document #: 38-03039 Rev. *H -150 -1.35 -150 150 -0.85 150 250 -150 -1.35 -150 150 -0.85 150 250 -150 -1.35 -150 150 -0.85 150 250 -180 -2.0 -180 180 -1.5 180 250 -200 -2.9 -200 200 -2.4 200 250 ps ns ps ms 2.8 0.22 3.0 0.25 3.3 0.28 4.0 0.35 5.0 0.38 ns ns 6.0 0.9 1.8 2.7 0.9 7.5 6.5 1.0 2.0 1.5 294 233 3.0 1.0 8.0 7.2 1.2 2.3 3.4 4.3 4.5 4.5 3.5 1.5 286 222 3.3 1.4 8.8 10.0 1.7 2.8 1.0 0.9 3.8 3.5 4.5 5.0 5.0 3.5 1.5 278 181 5.0 2.0 11.0 15.0 2.0 3.0 6.0 9.5 3.3 2.7 0 5.8 1.0 1.0 4.0 3.6 5.5 5.5 5.5 3.8 1.5 156 125 6.0 2.5 15.0 Min. Max. 7.2 4.5 4.5 6.0 10 3.6 3.0 0 6.0 1.2 1.2 4.5 6.4 8.0 8.0 8.0 6.0 1.5 104 83 Min. Combinatorial Mode Parameters 7.5 5.0 5.0 6.0 10.5 4.0 3.5 0 7.0 2.0 2.0 7.0 9.6 12 12 12 7.0 8.5 5.6 5.3 8.0 13 6.0 5.0 0 10 2.5 2.5 8.0 10 9.0 9.0 10 15 7.0 6.7 0 12 15 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz ns ns ns ns ns ns 200 Max. Min. 181 Max. Min. 125 Max. Min. 83 Max. Unit Synchronous Clocking Parameters Product Term Clocking Parameters Channel Interconnect Parameters Page 21 of 86 Delta39KTM ISRTM CPLD Family Switching Characteristics -- Parameter Values Over the Operating Range (continued) 233 Parameter tINDUTY fPLLO[14] fPLLI[14] fPLLVCO PSAPLLI fMPLLI JTAG Parameters tJCKH tJCKL tJCP tJSU tJH tJCO tJXZ tJZX 25 25 50 10 10 20 20 20 25 25 50 10 10 20 20 20 25 25 50 10 10 20 20 20 25 25 50 10 10 20 20 20 25 25 50 10 10 20 20 20 ns ns ns ns ns ns ns ns Min. 40 6.2 12.5 100 -0.3 Max. 60 266 133 266 +0.3 50 Min. 40 6.2 12.5 100 -0.3 200 Max. 60 266 133 266 +0.3 50 Min. 40 6.2 12.5 100 -0.3 181 Max. 60 266 133 266 +0.3 50 Min. 40 6.2 12.5 100 -0.3 125 Max. 60 200 100 266 +0.3 50 Min. 40 6.2 12.5 100 -0.3 83 Max. 60 200 100 266 +0.3 50 Unit % MHz MHz MHz % KHz Input and Output Standard Timing Delay Adjustments All the timing specifications in this data sheet are specified based on LVCMOS compliant inputs and outputs (fast slew rates).[15] Apply following adjustments if the inputs and outputs are configured to operate at other standards. Output Delay Adjustments Fast Slew Rate I/O Standard LVTTL - 2 mA LVTTL - 4 mA LVTTL - 6 mA LVTTL - 8 mA LVTTL - 12 mA LVTTL - 16 mA LVTTL - 24 mA LVCMOS LVCMOS3 LVCMOS2 LVCMOS18 3.3V PCI GTL+ SSTL3 I SSTL3 II tIOD 2.75 1.8 1.8 1.2 0.6 0.16 0 0 0.14 0.41 1.6 -0.14 0.02 [16] Slow Slew Rate (additional delay to fast slew rate) tIODSLOW 2.6 2.5 2.5 2.4 2.3 2.0 1.6 2.0 2.0 2.0 2.1 2.0 2.0 2.0 2.0 tEASLOW 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 tERSLOW 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 0 0 0 0 0 0 0 0 0 0 0.1 0 Input Delay Adjustments tIOIN 0 0 0 0 0 0 0 0 0.1 0.2 0.5 0 0.5 0.5 0.5 tCKIN 0 0 0 0 0 0 0 0 0.1 0.2 0.4 0 0.4 0.3 0.3 tIOREGPIN 0 0 0 0 0 0 0 0 0.2 0.4 0.3 0 0.2 0.3 0.3 tEA 0 0 0 0 0 0 0 0 0.05 0.1 0.7 0 0.6[16] 0.3 0.2 tER 0.9[16] 0.1 0 -0.15 -0.4 Notes: 14. Refer to page 11 and the application note titled "Delta39K PLL and Clock Tree" for details on the PLL operation. 15. For "slow slew rate" output delay adjustments, refer to Warp software's static timing analyzer results. 16. These delays are based on falling edge output. The rising edge delay depends on the size of pull-up resistor and termination voltage. Document #: 38-03039 Rev. *H Page 22 of 86 Delta39KTM ISRTM CPLD Family Output Delay Adjustments Fast Slew Rate I/O Standard SSTL2 I SSTL2 II HSTL I HSTL II HSTL III HSTL IV tIOD -0.02 -0.22 0.94 0.79 0.77 0.44 tEA 0.4 0.2 0.9 0.8 0.5 0.6 tER 0 0 0.5 0.5 0.1 0 Slow Slew Rate (additional delay to fast slew rate) tIODSLOW 2.0 2.0 2.0 2.0 2.0 2.0 tEASLOW 2.0 2.0 2.0 2.0 2.0 2.0 tERSLOW 2.0 2.0 2.0 2.0 2.0 2.0 Input Delay Adjustments tIOIN 0.9 0.9 0.5 0.5 0.5 0.5 tCKIN 0.5 0.5 0.5 0.5 0.5 0.5 tIOREGPIN 0.6 0.6 0.3 0.3 0.3 0.3 Cluster Memory Timing Parameter Values Over the Operating Range 233 Parameter tCLMAA tCLMPWE tCLMSA tCLMHA tCLMSD tCLMHD tCLMCYC1 tCLMCYC2 tCLMS tCLMH tCLMDV1 tCLMDV2 tCLMMACS1 tCLMMACS2 tMACCLMS1 tMACCLMS2 tCLMCLAA 7.7 4.5 3.6 6.0 6 5.5 1.8 0.9 5.5 0.4 9.5 5.0 2.8 0 10 7.0 8.0 5.0 4.0 6.5 6 Min. Max. 10.2 6 2.0 1.0 6.0 0.5 10 5.0 3.0 0 11 7.5 8.5 5.5 4.4 7.0 6.5 Min. Asynchronous Mode Parameters 11 6.5 2.2 1.1 6.5 0.6 10.5 5.5 3.8 0 12 8.0 12 8.0 6.6 10 10 12 10 3.2 1.8 10 0.9 15 8.0 4.0 0 17 10 15 10 8.0 12 12 17 12 4.0 2.0 12 1.0 20 10.0 5.0 0 20 15 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 200 Max. Min. 181 Max. Min. 125 Max. Min. 83 Max. Unit Synchronous Mode Parameters Internal Parameters Channel Memory Timing Parameter Values Over the Operating Range 233 Parameter tCHMAA tCHMPWE tCHMSA tCHMHA tCHMSD tCHMHD tCHMBA 5.5 1.8 0.9 5.5 0.4 8.5 Min. Max. 10 6.0 2.0 1.0 6.0 0.5 9.0 Min. Dual-Port Asynchronous Mode Parameters 11 6.5 2.2 1.1 6.5 0.6 10.0 12 10 3.2 1.8 10 0.9 14.0 17 12 4.0 2.0 12 1.0 16.0 20 ns ns ns ns ns ns ns 200 Max. Min. 181 Max. Min. 125 Max. Min. 83 Max. Unit Document #: 38-03039 Rev. *H Page 23 of 86 Delta39KTM ISRTM CPLD Family Channel Memory Timing Parameter Values Over the Operating Range (continued) Dual-Port Synchronous Mode Parameters tCHMCYC1 tCHMCYC2 tCHMS tCHMH tCHMDV1 tCHMDV2 tCHMBDV tCHMMACS1 tCHMMACS2 tMACCHMS1 tMACCHMS2 tCHMCLK tCHMFS tCHMFH tCHMFRDV tCHMMACS tMACCHMS tCHMFO tCHMMACF tCHMFRS tCHMFRSR tCHMFRSF tCHMSKEW1 tCHMSKEW2 tCHMSKEW3 Internal Parameters tCHMCHAA 6.5 7.0 7.5 10.0 13.0 ns 8.5 4.5 3.6 9.5 1.8 1.8 4.6 4.6 4.7 10.5 9 5.0 4.0 10.0 2.0 2.0 5.0 8.5 4.8 4.6 7.3 4.8 3.7 0 6.5 5.0 5.0 11 9.5 5.5 4.4 11.0 2.2 2.2 5.4 9.5 5.0 3.0 0 10 7.0 8.5 9.0 5.0 5.0 7.3 5.0 4.0 0 7.0 5.4 5.4 11.5 13 8.0 6.6 15.0 3.2 3.2 7.4 10 5.3 3.3 0 11 7.5 9.0 10.0 5.5 5.4 7.7 5.4 4.3 0 7.5 7.4 7.4 15 17 10 8.0 18.0 4.0 4.0 10.6 10 5.4 3.9 0 12 8.0 10.0 14.0 8.0 7.6 10.0 7.4 6.0 0 10.0 10.6 10.6 20 15 7.4 5.0 0 17 10 14.0 16.0 10 9.0 13.0 10.6 7.0 0 13.0 ns ns ns ns ns ns ns ns ns ns 20 10.6 6.0 0 20 15 16.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Synchronous FIFO Data Parameters Synchronous FIFO Flag Parameters Switching Waveforms Combinatorial Output INPUT tPD COMBINATORIAL OUTPUT Document #: 38-03039 Rev. *H Page 24 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Registered Output with Synchronous Clocking (Macrocell) INPUT tMCS tMCH SYNCHRONOUS CLOCK REGISTERED OUTPUT tMCCO Registered Input in I/O Cell DATA INPUT tIOS tIOH INPUT REGISTER CLOCK tIOCO REGISTERED OUTPUT Clock to Clock INPUT REGISTER CLOCK tICS tSCS MACROCELL REGISTER CLOCK PT Clock to PT Clock DATA INPUT tMCSPT tSCS2PT PT CLOCK Document #: 38-03039 Rev. *H Page 25 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Asynchronous Reset/Preset RESET/PRESET INPUT tPRO REGISTERED OUTPUT tPRR tPRW CLOCK Output Enable/Disable GLOBAL CONTROL INPUT tER OUTPUTS tEA Document #: 38-03039 Rev. *H Page 26 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Cluster Memory Asynchronous Timing READ ADDRESS (AT THE CLUSTER INPUT) WRITE READ WRITE ENABLE tCLMPWE INPUT tCLMCLAA OUTPUT tCLMCLAA Cluster Memory Asynchronous Timing 2 READ ADDRESS (AT THE I/O PIN) WRITE READ tCLMSA tCLMHA WRITE ENABLE tCLMPWE INPUT tCLMSD tCLMAA tCLMHD tCLMAA OUTPUT Document #: 38-03039 Rev. *H Page 27 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Cluster Memory Synchronous Flow-Through Timing READ GLOBAL CLOCK tCLMS tCLMH tCLMCYC1 WRITE READ ADDRESS tCLMS tCLMH tCLMS tCLMH WRITE ENABLE REGISTERED INPUT tCLMDV1 tCLMDV1 REGISTERED OUTPUT tCLMDV1 Cluster Memory Internal Clocking MACROCELL INPUT CLOCK tCLMMACS1 CLUSTER MEMORY INPUT CLOCK tCLMMACS2 tMACCLMS2 tMACCLMS1 CLUSTER MEMORY OUTPUT CLOCK Document #: 38-03039 Rev. *H Page 28 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Cluster Memory Output Register Timing (Asynchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 REGISTERED OUTPUT Cluster Memory Output Register Timing (Synchronous Inputs) ADDRESS WRITE ENABLE INPUT tCLMCYC2 GLOBAL CLOCK (INPUT REGISTER) tCLMS tCLMH GLOBAL CLOCK (OUTPUT REGISTER) tCLMDV2 REGISTERED OUTPUT Document #: 38-03039 Rev. *H Page 29 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory DP Asynchronous Timing ADDRESS An-1 An An+1 An+2 tCHMSA tCHMPWE tCHMHA WRITE ENABLE tCHMSD tCHMHD DATA INPUT Dn tCHMAA tCHMAA OUTPUT Dn-1 Dn Dn+1 Channel Memory Internal Clocking MACROCELL INPUT CLOCK tMACCHMS1 tCHMMACS1 CHANNEL MEMORY INPUT CLOCK tCHMMACS2 tMACCHMS2 CHANNEL MEMORY OUTPUT CLOCK Document #: 38-03039 Rev. *H Page 30 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory Internal Clocking 2 MACROCELL INPUT CLOCK tCHMMACS FIFO READ CLOCK tMACCHMS FIFO WRITE CLOCK tCHMMACF FIFO READ OR WRITE CLOCK Channel Memory DP SRAM Flow-Through R/W Timing CLOCK tCHMCYC1 tCHMS tCHMH ADDRESS An-1 An An+1 An+2 An+3 WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV1 tCHMDV1 tCHMDV1 tCHMDV1 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dn+3 Document #: 38-03039 Rev. *H Page 31 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory DP SRAM Pipeline R/W Timing CLOCK tCHMCYC2 tCHMS tCHMH ADDRESS An-1 An tCHMH An+1 An+2 An+3 tCHMS WRITE ENABLE tCHMS tCHMH DATA INPUT Dn-1 Dn+1 Dn+3 tCHMDV2 tCHMDV2 tCHMDV2 OUTPUT Dn-1 Dn Dn+1 Dn+2 Dual-Port Asynchronous Address Match Busy Signal ADDRESS A Bn An ADDRESS B An-1 An An+1 tCHMBA tCHMBA ADDRESS MATCH Document #: 38-03039 Rev. *H Page 32 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Dual-Port Synchronous Address Match Busy Signal CLOCK ADDRESS A An-1 An ADDRESS B Bn-1 tCHMS An tCHMS Bn+1 ADDRESS MATCH tCHMBDV tCHMBDV Document #: 38-03039 Rev. *H Page 33 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory Synchronous FIFO Empty/Write Timing PORT B CLOCK tCHMCLK tCHMFS tCHMFH WRITE ENABLE REGISTERED INPUT Dn+1 EMPTY FLAG (Active LOW) tCHMSKEW2 tCHMFO tCHMFO PORT A CLOCK READ ENABLE RE tCHMFRDV REGISTERED OUTPUT Document #: 38-03039 Rev. *H Page 34 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory Synchronous FIFO Full/Read Timing PORT A CLOCK tCHMCLK tCHMFS tCHMFH READ ENABLE tCHMFRDV REGISTERED OUTPUT FULL FLAG (Active LOW) tCHMSKEW1 tCHMFO tCHMFO PORT B CLOCK WRITE ENABLE tCHMS tCHMH REGISTERED INPUT Document #: 38-03039 Rev. *H Page 35 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory Synchronous FIFO Programmable Flag Timing PORT B CLOCK tCHMCLK tCHMFH tCHMFS WRITE ENABLE PROGRAMMABLE ALMOST EMPTY FLAG (active LOW) tCHMSKEW3 tCHMFO tCHMFO PORT A CLOCK tCHMFS READ ENABLE tCHMFH PORT B CLOCK tCHMCLK WRITE ENABLE tCHMFO PROGRAMMABLE ALMOST FULL FLAG (Active LOW) tCHMSKEW3 tCHMFO PORT A CLOCK READ ENABLE Document #: 38-03039 Rev. *H Page 36 of 86 Delta39KTM ISRTM CPLD Family Switching Waveforms (continued) Channel Memory Synchronous FIFO Master Reset Timing tCHMFRS MASTER RESET INPUT tCHMFRSR READ ENABLE / WRITE ENABLE tCHMFRSF EMPTY/FULL PROGRAMMABLE ALMOST EMPTY FLAGS tCHMFRSF HALF-FULL/ PROGRAMMABLE ALMOST FULL FLAGS tCHMFRSF REGISTERED OUTPUT CY 39 100 V 676 - 200 MB C Cypress Semiconductor ID Family Type 39 = Delta39K Family Gate Density 30=30k Usable Gates 50=50k Usable Gates 100=100k Usable Gates Operating Conditions Commercial 0C to +70C Industrial --40C to +85C 165 = 165k Usable Gates 200 = 200k Usable Gates Operating Reference Voltage V = 3.3V or 2.5V Supply Voltage Z = 1.8V Supply Voltage Pin Count 208 = 208 Leads 256 = 256 Balls 388 = 388 Balls 484 = 484 Balls 676 = 676 Balls Package Type N = Plastic Quad Flat Pack (PQFP) NT = Thermally Enhanced Quad Flat Pack (EQFP) BG = Ball Grid Array (BGA) BB = Fine-pitch Ball Grid Array (FBGA) 1.0-mm Lead Pitch MG = Self-Boot Solution -- Ball Grid Array MB = Self-Boot Solution -- Fine Pitch Ball Grid Array 1.0-mm Lead Pitch Speed 233 = 233 MHz 200 = 200 MHz 181 = 181 MHz 125 = 125 MHz 83 = 83 MHz Document #: 38-03039 Rev. *H Page 37 of 86 Delta39KTM ISRTM CPLD Family Delta39K Part Numbers (Ordering Information) Device 39K30 Speed (MHz) 233 Ordering Code CY39030V208-233NTC CY39030V256-233BBC CY39030V256-233MBC 125 CY39030V208-125NTC CY39030V256-125BBC CY39030V256-125MBC CY39030V208-125NTI CY39030V256-125BBI 83 CY39030V208-83NTC CY39030V256-83BBC CY39030V256-83MBC CY39030V208-83NTI CY39030V256-83BBI 39K50 233 CY39050V208-233NTC CY39050V256-233BBC CY39050V388-233MGC CY39050V484-233MBC 125 CY39050V208-125NTC CY39050V256-125BBC CY39050V388-125MGC CY39050V484-125MBC 39K50 125 83 CY39050V208-125NTI CY39050V256-125BBI CY39050V208-83NTC CY39050V256-83BBC CY39050V388-83MGC CY39050V484-83MBC CY39050V208-83NTI CY39050V256-83BBI 39K100 200 CY39100V208B-200NTC CY39100V256B-200BBC CY39100V484B-200BBC CY39100V388B-200MGC CY39100V676B-200MBC Package Name NT208 BB256 MB256 NT208 BB256 MB256 NT208 BB256 NT208 BB256 MB256 NT208 BB256 NT208 BB256 MG388 MB484 NT208 BB256 MG388 MB484 NT208 BB256 NT208 BB256 MG388 MB484 NT208 BB256 NT208 BB256 BB484 MG388 MB676 Package Type 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 256-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Plastic Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array / / Commercial / / Industrial Commercial / / Industrial / / Commercial / Industrial Commercial / Industrial / Self-Boot Solution Operating Range Commercial Document #: 38-03039 Rev. *H Page 38 of 86 Delta39KTM ISRTM CPLD Family Delta39K Part Numbers (Ordering Information) (continued) Device 39K100 Speed (MHz) 125 Ordering Code CY39100V208B-125NTC CY39100V256B-125BBC CY39100V484B-125BBC CY39100V388B-125MGC CY39100V676B-125MBC CY39100V208B-125NTI CY39100V256B-125BBI CY39100V484B-125BBI 83 CY39100V208B-83NTC CY39100V256B-83BBC CY39100V484B-83BBC CY39100V388B-83MGC CY39100V676B-83MBC CY39100V208B-83NTI CY39100V256B-83BBI CY39100V484B-83BBI 39K165 181 CY39165V208-181NTC CY39165V484-181BBC CY39165V388-181MGC CY39165V676-181MBC 125 CY39165V208-125NTC CY39165V484-125BBC CY39165V388-125MGC CY39165V676-125MBC CY39165V208-125NTI CY39165V484-125BBI 83 CY39165V208-83NTC CY39165V484-83BBC CY39165V388-83MGC CY39165V676-83MBC CY39165V208-83NTI CY39165V484-83BBI Package Name NT208 BB256 BB484 MG388 MB676 NT208 BB256 BB484 NT208 BB256 BB484 MG388 MB676 NT208 BB256 BB484 NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 NT208 BB484 MG388 MB676 NT208 BB484 Package Type 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 256-Lead Fine Pitch Ball Grid Array 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array / / Industrial Commercial / / Industrial / / Commercial Commercial / / Industrial Commercial / / Industrial Self-Boot Solution Operating Range Commercial Document #: 38-03039 Rev. *H Page 39 of 86 Delta39KTM ISRTM CPLD Family Delta39K Part Numbers (Ordering Information) (continued) Device 39K200 Speed (MHz) 181 Ordering Code CY39200V208-181NTC CY39200V484-181BBC CY39200V388-181MGC CY39200V676-181MBC 125 CY39200V208-125NTC CY39200V484-125BBC CY39200V388-125MGC CY39200V676-125MBC CY39200V208-125NTI CY39200V484-125BBI 83 CY39200V208-83NTC CY39200V484-83BBC CY39200V388-83MGC CY39200V676-83MBC CY39200V208-83NTI CY39200V484-83BBI Package Name NT208 BB484 MG388 MB676 NT208 BB484 MG388 MB676 NT208 BB484 NT208 BB484 MG388 MB676 NT208 BB484 Package Type 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array 388-Lead Ball Grid Array 676-Lead Fine Pitch Ball Grid Array 208-Lead Enhanced Quad Flat Pack 484-Lead Fine Pitch Ball Grid Array / / Industrial Commercial / / Industrial / / Commercial Self-Boot Solution Operating Range Commercial CPLD Boot EEPROM[17] Part Numbers (Ordering Information) Device 2 Mbit 1 Mbit 512 Kbit Speed (MHz) 15 10 15 10 15 10 Ordering Code AT17LV002-10JC AT17LV002-10JC AT17LV010-10JC AT17LV010-10JI AT17LV512-10JC AT17LV512-10JI Package Name 20J 20J 20J 20J 20J 20J Package Type 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Recommended ATMEL CPLD Boot EEPROM for corresponding Delta39K CPLDs CPLD Device 39K30 39K50 39K100 39K165 39K200 Note: 17. Refer to the data sheets at www.atmel.com for detailed architectural and timing information. Recommended boot EEPROM AT17LV512 AT17LV512 AT17LV010 AT17LV002 AT17LV002 Document #: 38-03039 Rev. *H Page 40 of 86 Delta39KTM ISRTM CPLD Family Package Diagrams 208-Lead Enhanced Quad Flat Pack (EQFP) NT208 51-85069-*B Document #: 38-03039 Rev. *H Page 41 of 86 Delta39KTM ISRTM CPLD Family Package Diagrams (continued) 388-Lead Ball Grid Array MG388 51-85103-*C Document #: 38-03039 Rev. *H Page 42 of 86 Delta39KTM ISRTM CPLD Family Package Diagrams (continued) 256-Ball FBGA (17 x 17 mm) BB256 TOP VIEW O0.05 M C O0.25 M C A B O0.450.05(256X)-CPLD DEVICES (37K & 39K) O0.500.05(256X)-ALL OTHER DEVICES 1 A B C 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 15 14 13 12 11 10 9 8 7 6 5 4 3 BOTTOM VIEW PIN 1 CORNER 2 1 A B C PIN 1 CORNER E F G 1.00 D D E F G J K L 15.00 H 17.000.10 H J K L N P R T 7.50 M M N P R T 1.00 B 0.700.05 7.50 0.15 C 15.00 A A SEATING PLANE A1 +0.10 -0.05 0.25 C 17.000.10 0.20(4X) C REFERENCE JEDEC MO-192 A1 0.36 0.56 A 1.40 MAX. 1.60 MAX. 0.35 51-85108-*D Document #: 38-03039 Rev. *H Page 43 of 86 Delta39KTM ISRTM CPLD Family Package Diagrams (continued) 484-ball FBGA (23 mm x 23 mm x 1.6 mm) BB484 BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K L M N P R T U V W Y AA AB 11 12 13 14 15 16 17 18 19 20 21 22 22 21 20 19 18 O0.05 M C O0.25 M C A B O0.600.10(484X) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB 1.00 10.50 21.00 0.700.05 0.25 C 0.20 C A1 CORNER 23.000.10 21.00 10.50 A 1.00 B 0.10(4X) 23.000.10 SEATING PLANE 0.56 0.500.10 1.90 MAX C 51-85124-*D Document #: 38-03039 Rev. *H Page 44 of 86 Delta39KTM ISRTM CPLD Family Package Diagrams (continued) 676-Ball FBGA (27 x 27 x 1.6 mm) BB676/MB676 51-85125-*B Pin Tables Table 8. Pin Definition Table Pin Name GCLK0-3 GCTL0-3 GND IO/VREF0 IO/VREF1 IO/VREF2 IO/VREF3 IO/VREF4 IO/VREF5 IO/VREF6 IO/VREF7 IO IO6/Lock MSEL Function Input Input Ground Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Global Clock signals 0 through 3 Global Control signals 0 through 3 Ground Dual function pin: IO or Reference Voltage for Bank 0 Dual function pin: IO or Reference Voltage for Bank 1 Dual function pin: IO or Reference Voltage for Bank 2 Dual function pin: IO or Reference Voltage for Bank 3 Dual function pin: IO or Reference Voltage for Bank 4 Dual function pin: IO or Reference Voltage for Bank 5 Dual function pin: IO or Reference Voltage for Bank 6 Dual function pin: IO or Reference Voltage for Bank 7 Input or Output pin Dual function pin: IO in Bank 6 or PLL lock output signal Mode Select Pin (see Table 9) Description Document #: 38-03039 Rev. *H Page 45 of 86 Delta39KTM ISRTM CPLD Family Table 8. Pin Definition Table Pin Name Reconfig TCLK TDI TDO TMS VCC VCCIO0 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCJTAG VCCCNFG VCCPLL[18] VCCPRG Config_Done CCLK CCE Data Reset Function Input Input Input Output Input Power Power Power Power Power Power Power Power Power Power Power Power Power Output Output Output Input Output Pin to start configuration of Delta39K JTAG Test Clock JTAG Test Data In JTAG Test Data Out JTAG Test Mode Select Operating Voltage VCC for I/O bank 0 VCC for I/O bank 1 VCC for I/O bank 2 VCC for I/O bank 3 VCC for I/O bank 4 VCC for I/O bank 5 VCC for I/O bank 6 VCC for I/O bank 7 VCC for JTAG pins VCC for Configuration port VCC for PLL VCC for programming the Self-BootTM solution embedded boot PROM Flag indicating that configuration is complete Configuration Clock for serial interface with the external boot PROM Chip select for the external boot PROM (active low) Pin to receive configuration data from the external boot PROM Reset signal to interface with the external boot PROM Table 10. I/O Banks for Global Clock and Global Control Pins (in all densities and packages) GCLK[0] GCTL[0] Bank Number Table 11. 208 EQFP/PQFP Pin Table Pin 1 2 3 4 5 6 7 8 9 10 CY39030 GCTL0 GND GCLK0 GND IO0 IO0 IO0 IO/VREF0 IO0 IO0 CY39050 GCTL0 GND GCLK0 GND IO0 IO0 IO0 IO/VREF0 IO0 IO0 CY39100 GCTL0 GND GCLK0 GND IO0 IO0 IO0 IO/VREF0 IO0 IO0 CY39165 GCTL0 GND GCLK0 GND IO0 IO0 IO0 IO/VREF0 IO0 IO0 CY39200 GCTL0 GND GCLK0 GND IO0 IO0 IO0 IO/VREF0 IO0 IO0 0 GCLK[1] GCTL[1] 5 GCLK[2] GCTL[2] 6 GCLK[3] GCTL[3] 7 Description Table 9. Mode Select (MSEL) Pin Connectivity Table GND VCCCNFG Delta39K - Self-BootTM Solution Delta39K - with external boot PROM 11 VCCIO0 VCCIO0 VCCIO0 VCCIO0 VCCIO0 Note: 18. The PLL is available in Delta39K `V' devices (2.5V/3.3V) and not in Delta39K `Z' devices (1.8V). In Delta39K `Z' devices, connect VCCPLL to VCC. Document #: 38-03039 Rev. *H Page 46 of 86 Delta39KTM ISRTM CPLD Family Table 11. 208 EQFP/PQFP Pin Table (continued) Pin 12 13 14 15 16 17 18 19 20 21[19] 22[19] 23 24 25 26 27[19] 28 29 30[19] 31[19] 32[19] 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 CY39030 IO0 IO0 IO0 IO0 IO/VREF0 IO0 IO0 IO0 VCCIO0 IO0 IO0 VCC GND NC NC IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCIO1 GND IO1 IO1 IO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCPRG VCCIO1 GND IO1 IO/VREF1 IO1 IO1 VCCCNFG Data Config_Done Reset CY39050 IO0 IO0 IO0 IO0 IO/VREF0 IO0 IO0 IO0 VCCIO0 IO0 IO0 VCC GND NC NC IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCIO1 GND IO1 IO1 IO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCPRG VCCIO1 GND IO1 IO/VREF1 IO1 IO1 VCCCNFG Data Config_Done Reset CY39100 IO0 IO0 IO0 IO0 IO/VREF0 IO0 IO0 IO0 VCCIO0 IO0 IO0 VCC GND VCC GND IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCIO1 GND IO1 IO1 IO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCPRG VCCIO1 GND IO1 IO/VREF1 IO1 IO1 VCCCNFG Data Config_Done Reset CY39165 IO0 IO0 IO0 IO0 IO/VREF0 IO0 IO0 IO0 VCCIO0 IO0 IO0 VCC GND VCC GND IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCIO1 GND IO1 IO1 IO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCPRG VCCIO1 GND IO1 IO/VREF1 IO1 IO1 VCCCNFG Data Config_Done Reset CY39200 IO0 IO0 IO0 IO0 IO/VREF0 IO0 IO0 IO0 VCCIO0 IO0 IO0 VCC GND VCC GND IO/VREF0 VCCIO0 VCCIO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCIO1 GND IO1 IO1 IO1 IO/VREF1 IO1 IO1 IO1 IO1 VCCPRG VCCIO1 GND IO1 IO/VREF1 IO1 IO1 VCCCNFG Data Config_Done Reset Page 47 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 11. 208 EQFP/PQFP Pin Table (continued) Pin 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81[19] 82[19] 83[19] 84 85 86[19] 87[19] 88[19] 89 90 91 92 93 94 95 96 97 98 99 CY39030 Reconfig CCE CCLK VCCCNFG MSEL IO2 IO2 IO2 IO/VREF2 IO2 VCCIO2 GND IO2 IO2 IO2 IO2 IO/VREF2 GND VCCIO2 VCC GND NC NC IO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 VCCIO3 IO3 IO3 IO/VREF3 VCCIO3 GND IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 VCCIO3 IO3 CY39050 Reconfig CCE CCLK VCCCNFG MSEL IO2 IO2 IO2 IO/VREF2 IO2 VCCIO2 GND IO2 IO2 IO2 IO2 IO/VREF2 GND VCCIO2 VCC GND NC NC IO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 VCCIO3 IO3 IO3 IO/VREF3 VCCIO3 GND IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 VCCIO3 IO3 CY39100 Reconfig CCE CCLK VCCCNFG MSEL IO2 IO2 IO2 IO/VREF2 IO2 VCCIO2 GND IO2 IO2 IO2 IO2 IO/VREF2 GND VCCIO2 VCC GND VCC GND IO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 VCCIO3 IO3 IO3 IO/VREF3 VCCIO3 GND IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 VCCIO3 IO3 CY39165 Reconfig CCE CCLK VCCCNFG MSEL IO2 IO2 IO2 IO/VREF2 IO2 VCCIO2 GND IO2 IO2 IO2 IO2 IO/VREF2 GND VCCIO2 VCC GND VCC GND IO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 VCCIO3 IO3 IO3 IO/VREF3 VCCIO3 GND IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 VCCIO3 IO3 CY39200 Reconfig CCE CCLK VCCCNFG MSEL IO2 IO2 IO2 IO/VREF2 IO2 VCCIO2 GND IO2 IO2 IO2 IO2 IO/VREF2 GND VCCIO2 VCC GND VCC GND IO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 VCCIO3 IO3 IO3 IO/VREF3 VCCIO3 GND IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 VCCIO3 IO3 Page 48 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 11. 208 EQFP/PQFP Pin Table (continued) Pin 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122[19] 123[19] 124 125 126[19] 127 128 129 130 131 132 133[19] 134[19] 135 [19] CY39030 GND IO3 IO3 IO3 IO/VREF3 IO4 IO4 IO4 IO/VREF4 IO4 IO4 VCCIO4 GND IO4 VCCPRG IO4 IO/VREF4 IO4 IO4 IO4 IO4 IO4 IO/VREF4 IO4 VCCIO4 GND IO4 VCC GND NC NC VCCIO4 VCCIO5 IO5 IO5 IO/VREF5 IO5 IO5 VCCIO5 IO5 IO5 IO5 IO/VREF5 IO5 CY39050 GND IO3 IO3 IO3 IO/VREF3 IO4 IO4 IO4 IO/VREF4 IO4 IO4 VCCIO4 GND IO4 VCCPRG IO4 IO/VREF4 IO4 IO4 IO4 IO4 IO4 IO/VREF4 IO4 VCCIO4 GND IO4 VCC GND NC NC VCCIO4 VCCIO5 IO5 IO5 IO/VREF5 IO5 IO5 VCCIO5 IO5 IO5 IO5 IO/VREF5 IO5 CY39100 GND IO3 IO3 IO3 IO/VREF3 IO4 IO4 IO4 IO/VREF4 IO4 IO4 VCCIO4 GND IO4 VCCPRG IO4 IO/VREF4 IO4 IO4 IO4 IO4 IO4 IO/VREF4 IO4 VCCIO4 GND IO4 VCC GND VCC GND VCCIO4 VCCIO5 IO5 IO5 IO/VREF5 IO5 IO5 VCCIO5 IO5 IO5 IO5 IO/VREF5 IO5 CY39165 GND IO3 IO3 IO3 IO/VREF3 IO4 IO4 IO4 IO/VREF4 IO4 IO4 VCCIO4 GND IO4 VCCPRG IO4 IO/VREF4 IO4 IO4 IO4 IO4 IO4 IO/VREF4 IO4 VCCIO4 GND IO4 VCC GND VCC GND VCCIO4 VCCIO5 IO5 IO5 IO/VREF5 IO5 IO5 VCCIO5 IO5 IO5 IO5 IO/VREF5 IO5 CY39200 GND IO3 IO3 IO3 IO/VREF3 IO4 IO4 IO4 IO/VREF4 IO4 IO4 VCCIO4 GND IO4 VCCPRG IO4 IO/VREF4 IO4 IO4 IO4 IO4 IO4 IO/VREF4 IO4 VCCIO4 GND IO4 VCC GND VCC GND VCCIO4 VCCIO5 IO5 IO5 IO/VREF5 IO5 IO5 VCCIO5 IO5 IO5 IO5 IO/VREF5 IO5 Page 49 of 86 136 137 138 139 140 141 142 143 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 11. 208 EQFP/PQFP Pin Table (continued) Pin 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183[19] 184[19] 185 [19] CY39030 IO5 IO5 IO5 IO5 VCCIO5 IO/VREF5 IO5 IO5 GND GCLK1 GND GCTL1 TDO TCLK TDI VCCJTAG GCLK2 GND TMS GCTL2 IO6 IO6 IO6 IO/VREF6 IO6 VCCIO6 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND VCCIO6 VCCPLL GND VCC GND IO/VREF6 IO6 IO6/Lock VCCIO6 VCCIO7 CY39050 IO5 IO5 IO5 IO5 VCCIO5 IO/VREF5 IO5 IO5 GND GCLK1 GND GCTL1 TDO TCLK TDI VCCJTAG GCLK2 GND TMS GCTL2 IO6 IO6 IO6 IO/VREF6 IO6 VCCIO6 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND VCCIO6 VCCPLL GND VCC GND IO/VREF6 IO6 IO6/Lock VCCIO6 VCCIO7 CY39100 IO5 IO5 IO5 IO5 VCCIO5 IO/VREF5 IO5 IO5 GND GCLK1 GND GCTL1 TDO TCLK TDI VCCJTAG GCLK2 GND TMS GCTL2 IO6 IO6 IO6 IO/VREF6 IO6 VCCIO6 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND VCCIO6 VCCPLL GND VCC GND IO/VREF6 IO6 IO6/Lock VCCIO6 VCCIO7 CY39165 IO5 IO5 IO5 IO5 VCCIO5 IO/VREF5 IO5 IO5 GND GCLK1 GND GCTL1 TDO TCLK TDI VCCJTAG GCLK2 GND TMS GCTL2 IO6 IO6 IO6 IO/VREF6 IO6 VCCIO6 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND VCCIO6 VCCPLL GND VCC GND IO/VREF6 IO6 IO6/Lock VCCIO6 VCCIO7 CY39200 IO5 IO5 IO5 IO5 VCCIO5 IO/VREF5 IO5 IO5 GND GCLK1 GND GCTL1 TDO TCLK TDI VCCJTAG GCLK2 GND TMS GCTL2 IO6 IO6 IO6 IO/VREF6 IO6 VCCIO6 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND VCCIO6 VCCPLL GND VCC GND IO/VREF6 IO6 IO6/Lock VCCIO6 VCCIO7 Page 50 of 86 186 187 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 11. 208 EQFP/PQFP Pin Table (continued) Pin 188[19] 189[19] 190[19] 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 CY39030 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 VCCIO7 IO7 IO/VREF7 IO7 IO7 IO7 GND GCLK3 GND GCTL3 CY39050 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 VCCIO7 IO7 IO/VREF7 IO7 IO7 IO7 GND GCLK3 GND GCTL3 CY39100 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 VCCIO7 IO7 IO/VREF7 IO7 IO7 IO7 GND GCLK3 GND GCTL3 CY39165 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 VCCIO7 IO7 IO/VREF7 IO7 IO7 IO7 GND GCLK3 GND GCTL3 CY39200 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 VCCIO7 IO7 IO/VREF7 IO7 IO7 IO7 GND GCLK3 GND GCTL3 Table 12. 388 BGA Pin Table Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 [19] CY39050 GND NC IO7 IO7 IO7 IO7 IO7 NC IO7 IO7 IO/VREF7 IO7 IO7 IO6 IO6 GND IO6 IO6 CY39100 GND IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO/VREF7 IO7 IO7 IO6 IO6 GND IO6 IO6 CY39165 GND IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO/VREF7 IO7 IO7 IO6 IO6 GND IO6 IO6 CY39200 GND IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO/VREF7 IO7 IO7 IO6 IO6 GND IO6 IO6 A14[19] A15 A16 A17 A18 Note: 19. Capacitance on these I/O pins meets the PCI spec (rev. 2.2), which requires IDSEL pin in a PCI design to have capacitance less than or equal to 8 pf. In the document titled "Delta39K CPLD Family data sheet", this spec is defined as CPCI. All other I/O pins have a capacitance less than or equal to 10 pf. Document #: 38-03039 Rev. *H Page 51 of 86 Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13[19] B14[19] B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 CY39050 NC NC IO6 IO/VREF6 IO6 IO6 IO6 GND IO7 NC NC NC IO7 IO/VREF7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO7 IO6 IO6 IO6 IO6/Lock IO6 IO6 IO/VREF6 IO6 NC NC IO6 IO6 IO6 IO0 IO/VREF7 NC IO7 IO7 NC IO7 IO7 IO7 IO7 CY39100 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND IO7 IO7 IO7 IO/VREF7 IO7 IO/VREF7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO7 IO6 IO6 IO6 IO6/Lock IO6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO0 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 CY39165 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND IO7 IO7 IO7 IO/VREF7 IO7 IO/VREF7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO7 IO6 IO6 IO6 IO6/Lock IO6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO0 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 CY39200 IO6 IO6 IO6 IO/VREF6 IO6 IO6 IO6 GND IO7 IO7 IO7 IO/VREF7 IO7 IO/VREF7 IO7 IO7 IO7 IO/VREF7 IO7 IO7 IO7 IO6 IO6 IO6 IO6/Lock IO6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO0 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 Page 52 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin C11 C12 C13[19] C14[19] C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 CY39050 IO7 IO7 IO7 IO6 IO/VREF6 IO6 NC IO6 IO6 IO6 IO6 NC NC IO6 IO/VREF6 IO6 IO0 IO0 IO/VREF0 IO7 GCTL3 NC GCLK3 VCCIO7 VCCIO7 VCCIO7 IO7 VCCIO7 VCC VCCIO6 VCCIO6 IO6 VCCPLL VCCIO6 VCCIO6 GCLK2 NC GCTL2 NC IO5 TMS TCLK IO0 IO0 CY39100 IO7 IO7 IO7 IO6 IO/VREF6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 IO6 IO0 IO0 IO/VREF0 IO7 GCTL3 IO7 GCLK3 VCCIO7 VCCIO7 VCCIO7 IO7 VCCIO7 VCC VCCIO6 VCCIO6 IO6 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 IO6 IO5 TMS TCLK IO0 IO0 CY39165 IO7 IO7 IO7 IO6 IO/VREF6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 IO6 IO0 IO0 IO/VREF0 IO7 GCTL3 IO7 GCLK3 VCCIO7 VCCIO7 VCCIO7 IO7 VCCIO7 VCC VCCIO6 VCCIO6 IO6 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 IO6 IO5 TMS TCLK IO0 IO0 CY39200 IO7 IO7 IO7 IO6 IO/VREF6 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 IO6 IO0 IO0 IO/VREF0 IO7 GCTL3 IO7 GCLK3 VCCIO7 VCCIO7 VCCIO7 IO7 VCCIO7 VCC VCCIO6 VCCIO6 IO6 VCCPLL VCCIO6 VCCIO6 GCLK2 IO/VREF6 GCTL2 IO6 IO5 TMS TCLK IO0 IO0 Page 53 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin E3 E4 E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4 J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 CY39050 IO0 GCTL0 GCLK1 IO5 TDI TDO NC NC NC IO0 NC IO5 IO5 IO5 IO0 IO0 IO/VREF0 GCLK0 GCTL1 IO/VREF5 IO5 IO5 IO0 NC NC VCCIO0 VCCJTAG IO5 IO5 IO5 NC NC NC VCCIO0 VCCIO5 NC IO5 IO5 NC NC NC VCC VCCIO5 IO5 CY39100 IO0 GCTL0 GCLK1 IO5 TDI TDO IO0 IO0 IO0 IO0 IO5 IO5 IO5 IO5 IO0 IO0 IO/VREF0 GCLK0 GCTL1 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 VCCJTAG IO5 IO5 IO5 IO0 IO/VREF0 IO0 VCCIO0 VCCIO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCC VCCIO5 IO5 CY39165 IO0 GCTL0 GCLK1 IO5 TDI TDO IO0 IO0 IO0 IO0 IO5 IO5 IO5 IO5 IO0 IO0 IO/VREF0 GCLK0 GCTL1 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 VCCJTAG IO5 IO5 IO5 IO0 IO/VREF0 IO0 VCCIO0 VCCIO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCC VCCIO5 IO5 CY39200 IO0 GCTL0 GCLK1 IO5 TDI TDO IO0 IO0 IO0 IO0 IO5 IO5 IO5 IO5 IO0 IO0 IO/VREF0 GCLK0 GCTL1 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 VCCJTAG IO5 IO5 IO5 IO0 IO/VREF0 IO0 VCCIO0 VCCIO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCC VCCIO5 IO5 Page 54 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin K25 K26 L1 L2 L3 L4 L11 L12 L13 L14 L15 L16 L23 L24 L25 L26 M1 M2[19] M3[19] M4 M11 M12 M13 M14 M15 M16 M23 M24 M25 M26 N1 N2 N3[19] N4[19] N11 N12 N13 N14 N15 N16 N23[19] N24 N25 N26 CY39050 NC NC IO0 IO0 IO0 IO0 GND GND GND GND GND GND NC IO/VREF5 NC NC IO0 IO0 IO0 VCCIO0 GND GND GND GND GND GND VCCIO5 NC NC NC NC IO/VREF0 IO0 IO1 GND GND GND GND GND GND IO5 IO5 IO5 IO/VREF5 CY39100 IO5 IO5 IO0 IO0 IO0 IO0 GND GND GND GND GND GND IO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 GND GND GND GND GND GND VCCIO5 IO5 IO5 IO5 VCC IO/VREF0 IO0 IO1 GND GND GND GND GND GND IO5 IO5 IO5 IO/VREF5 CY39165 IO5 IO5 IO0 IO0 IO0 IO0 GND GND GND GND GND GND IO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 GND GND GND GND GND GND VCCIO5 IO5 IO5 IO5 VCC IO/VREF0 IO0 IO1 GND GND GND GND GND GND IO5 IO5 IO5 IO/VREF5 CY39200 IO5 IO5 IO0 IO0 IO0 IO0 GND GND GND GND GND GND IO5 IO/VREF5 IO5 IO5 IO0 IO0 IO0 VCCIO0 GND GND GND GND GND GND VCCIO5 IO5 IO5 IO5 VCC IO/VREF0 IO0 IO1 GND GND GND GND GND GND IO5 IO5 IO5 IO/VREF5 Page 55 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin P1 P2 P3[19] P4 [19] CY39050 IO1 IO/VREF1 IO1 IO1 GND GND GND GND GND GND VCC IO5 IO5 NC IO1 IO1 NC VCCIO1 GND GND GND GND GND GND VCCIO4 IO4 IO4 NC NC NC NC NC GND GND GND GND GND GND IO4 IO4 IO/VREF4 IO4 NC NC CY39100 IO1 IO/VREF1 IO1 IO1 GND GND GND GND GND GND VCC IO5 IO5 VCC IO1 IO1 IO1 VCCIO1 GND GND GND GND GND GND VCCIO4 IO4 IO4 IO5 IO1 IO1 IO/VREF1 IO1 GND GND GND GND GND GND IO4 IO4 IO/VREF4 IO4 IO1 IO1 CY39165 IO1 IO/VREF1 IO1 IO1 GND GND GND GND GND GND VCC IO5 IO5 VCC IO1 IO1 IO1 VCCIO1 GND GND GND GND GND GND VCCIO4 IO4 IO4 IO5 IO1 IO1 IO/VREF1 IO1 GND GND GND GND GND GND IO4 IO4 IO/VREF4 IO4 IO1 IO1 CY39200 IO1 IO/VREF1 IO1 IO1 GND GND GND GND GND GND VCC IO5 IO5 VCC IO1 IO1 IO1 VCCIO1 GND GND GND GND GND GND VCCIO4 IO4 IO4 IO5 IO1 IO1 IO/VREF1 IO1 GND GND GND GND GND GND IO4 IO4 IO/VREF4 IO4 IO1 IO1 Page 56 of 86 P11 P12 P13 P14 P15 P16 P23 P24[19] P25[19] P26 R1 R2 R3 R4 R11 R12 R13 R14 R15 R16 R23 R24[19] R25[19] R26 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T23[19] T24 T25 T26 U1 U2 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin U3 U4 U23 U24 U25 U26 V1 V2 V3 V4 V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB23 AB24 CY39050 NC VCCPRG VCCPRG IO4 IO4 NC NC NC IO1 VCCIO1 VCCIO4 NC NC NC IO1 IO1 IO/VREF1 VCCIO1 VCCIO4 NC NC NC IO1 IO1 IO1 IO1 NC NC NC IO4 IO1 IO1 IO/VREF1 IO1 IO4 IO4 IO/VREF4 IO4 VCCCNFG Config_Done IO1 IO1 IO4 IO4 CY39100 IO1 VCCPRG VCCPRG IO4 IO4 IO4 IO1 IO1 IO1 VCCIO1 VCCIO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 VCCIO1 VCCIO4 IO4 IO/VREF4 IO4 IO1 IO1 IO1 IO1 IO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 IO1 IO4 IO4 IO/VREF4 IO4 VCCCNFG Config_Done IO1 IO1 IO4 IO4 CY39165 IO1 VCCPRG VCCPRG IO4 IO4 IO4 IO1 IO1 IO1 VCCIO1 VCCIO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 VCCIO1 VCCIO4 IO4 IO/VREF4 IO4 IO1 IO1 IO1 IO1 IO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 IO1 IO4 IO4 IO/VREF4 IO4 VCCCNFG Config_Done IO1 IO1 IO4 IO4 CY39200 IO1 VCCPRG VCCPRG IO4 IO4 IO4 IO1 IO1 IO1 VCCIO1 VCCIO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 VCCIO1 VCCIO4 IO4 IO/VREF4 IO4 IO1 IO1 IO1 IO1 IO4 IO4 IO4 IO4 IO1 IO1 IO/VREF1 IO1 IO4 IO4 IO/VREF4 IO4 VCCCNFG Config_Done IO1 IO1 IO4 IO4 Page 57 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14[19] AD15[19] AD16 CY39050 IO4 IO4 Data Reconfig IO2 IO2 IO2 IO2 NC VCCIO2 VCCIO2 VCCCNFG IO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 IO3 NC VCCIO3 VCCIO3 IO3 IO3 IO3 IO/VREF4 IO4 IO4 IO4 Reset CCLK IO/VREF2 IO2 IO/VREF2 IO2 NC NC IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO3 IO3 CY39100 IO4 IO4 Data Reconfig IO2 IO2 IO2 IO2 IO2 VCCIO2 VCCIO2 VCCCNFG IO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 IO3 VCC VCCIO3 VCCIO3 IO3 IO3 IO3 IO/VREF4 IO4 IO4 IO4 Reset CCLK IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO3 IO3 CY39165 IO4 IO4 Data Reconfig IO2 IO2 IO2 IO2 IO2 VCCIO2 VCCIO2 VCCCNFG IO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 IO3 VCC VCCIO3 VCCIO3 IO3 IO3 IO3 IO/VREF4 IO4 IO4 IO4 Reset CCLK IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO3 IO3 CY39200 IO4 IO4 Data Reconfig IO2 IO2 IO2 IO2 IO2 VCCIO2 VCCIO2 VCCCNFG IO2 VCCIO2 VCCIO2 VCCIO3 VCCIO3 IO3 VCC VCCIO3 VCCIO3 IO3 IO3 IO3 IO/VREF4 IO4 IO4 IO4 Reset CCLK IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO/VREF2 IO2 IO2 IO/VREF2 IO2 IO3 IO3 Page 58 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13[19] AE14 [19] CY39050 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 NC IO/VREF3 IO3 CCE MSEL IO2 IO2 IO2 NC NC IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF3 IO3 IO3 IO3 IO3 IO/VREF3 NC IO3 NC NC IO3 IO3 GND IO2 IO2 IO2 IO2 NC NC NC CY39100 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 CCE MSEL IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND IO2 IO2 IO2 IO2 IO2 IO2 IO2 CY39165 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 CCE MSEL IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND IO2 IO2 IO2 IO2 IO2 IO2 IO2 CY39200 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 CCE MSEL IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND IO2 IO2 IO2 IO2 IO2 IO2 IO2 Page 59 of 86 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 12. 388 BGA Pin Table (continued) Pin AF9 AF10 AF11 AF12 AF13 AF14[19] AF15[19] AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 CY39050 NC IO2 GND IO2 VCC IO3 IO3 IO3 IO3 IO3 IO3 IO3 NC NC IO3 NC NC GND CY39100 IO2 IO2 GND IO2 VCC IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND CY39165 IO2 IO2 GND IO2 VCC IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND CY39200 IO2 IO2 GND IO2 VCC IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 IO3 GND Table 13. 256 FBGA Pin Table Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 CY39030 GND IO7 IO7 IO7 IO7 IO/VREF7 NC IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO0 GND IO7 IO7 IO7 VCCIO7 VCC CY39050 GND IO7 IO7 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO0 GND IO7 IO7 IO7 VCCIO7 VCC CY39100 GND IO7 IO7 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO0 GND IO7 IO7 IO7 VCCIO7 VCC Document #: 38-03039 Rev. *H Page 60 of 86 Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8[19] C9 [19] CY39030 IO/VREF7 NC VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 NC IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 NC IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO0 IO0 IO0 CY39050 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO0 IO0 IO0 CY39100 IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO0 IO0 IO0 Page 61 of 86 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8[19] D9[19] D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin E4 E5 E6 E7 E8[19] E9[19] E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 Document #: 38-03039 Rev. *H CY39030 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO0 NC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 NC CY39050 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO0 NC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 NC CY39100 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO0 VCC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC Page 62 of 86 Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin G16 H1[19] H2[19] H3 [19] CY39030 IO5 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 CY39050 IO5 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 CY39100 IO5 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 Page 63 of 86 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14[19] H15[19] H16[19] J1 J2 J3 [19] J4[19] J5[19] J6 J7 J8 J9 J10 J11 J12[19] J13[19] J14[19] J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8[19] L9[19] L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8[19] M9[19] M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 Document #: 38-03039 Rev. *H CY39030 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO1 NC VCCIO1 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 CY39050 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO1 NC VCCIO1 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 CY39100 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO1 VCC VCCIO1 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 Page 64 of 86 Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin N8[19] N9[19] N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 Document #: 38-03039 Rev. *H CY39030 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 GND Reset IO2 CY39050 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 GND Reset IO2 CY39100 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 GND Reset IO2 Page 65 of 86 Delta39KTM ISRTM CPLD Family Table 13. 256 FBGA Pin Table (continued) Pin T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Table 14. 484 FBGA Pin Table Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 B1 B2 B3 B4 B5 B6 CY39050 GND GND NC NC IO7 IO7 NC IO7 IO7 IO7 GND GND IO6 IO6 IO6 NC IO6 IO6 NC NC GND GND GND GND NC VCCIO7 NC IO7 CY39100 GND GND NC NC IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 NC NC GND GND GND GND NC VCCIO7 IO7 IO7 CY39165 GND GND IO/VREF7 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 NC NC GND GND GND GND IO7 VCCIO7 IO7 IO7 CY39200 GND GND IO/VREF7 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 IO6 GND GND GND GND IO7 VCCIO7 IO7 IO7 CY39030 IO2 IO2 IO/VREF2 NC IO2 IO2 NC IO/VREF3 IO3 IO3 IO3 IO3 GND CY39050 IO2 IO2 IO/VREF2 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND CY39100 IO2 IO2 IO/VREF2 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND Document #: 38-03039 Rev. *H Page 66 of 86 Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D5 D6 CY39050 NC IO/VREF7 NC IO7 IO7 IO6 IO6 NC IO/VREF6 NC IO6 IO6 VCCIO6 NC GND GND NC NC NC NC NC IO7 NC IO7 IO7 IO/VREF7 IO7 IO6 NC IO6 IO6 NC IO6 IO6 IO6 NC NC NC NC VCCIO0 NC GND NC NC CY39100 IO7 IO/VREF7 NC IO7 IO7 IO6 IO6 NC IO/VREF6 IO6 IO6 IO6 VCCIO6 NC GND GND NC NC NC IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 NC NC NC NC VCCIO0 NC GND IO7 IO7 CY39165 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO6 IO6 VCCIO6 IO/VREF6 IO6[20] IO6 IO6 VCCIO6 NC GND GND IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6[20] IO6 IO6 IO6 IO6 NC NC NC IO/VREF0 VCCIO0 IO0 GND IO7 IO7 CY39200 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO6 IO6 VCCIO6 IO/VREF6 IO6 IO6 IO6 VCCIO6 IO6 GND GND IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF0 VCCIO0 IO0 GND IO7 IO7 Page 67 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 CY39050 IO7 IO7 IO/VREF7 NC IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 NC NC IO6 GND NC VCCIO5 NC NC NC NC IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 NC VCCPLL VCCIO6 NC NC NC GND TDO NC NC NC NC NC IO0 IO0 IO0 GND CY39100 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND NC VCCIO5 NC NC NC NC IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO NC NC NC NC IO0 IO0 IO0 IO0 GND CY39165 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO5 VCCIO5 IO/VREF5 IO0 IO0 IO0 IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6[19] IO6 IO6 GND TDO IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 GND CY39200 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO5 VCCIO5 IO/VREF5 IO0 IO0 IO0 IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 GND Page 68 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin F7 F8 F9 F10 F11[19] F12 [19] CY39050 IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 NC GND TDI IO5 IO5 NC NC NC IO0 NC IO0 IO0 IO0 GND IO7 NC IO7 IO7 IO6 IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 NC NC IO0 IO0 IO0 NC NC CY39100 IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO5 IO5 NC NC IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 NC NC IO0 IO0 IO0 IO0 IO0 CY39165 IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6[20] IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 IO0 CY39200 IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 IO5 IO0 IO0 IO0 IO0 IO0 IO0 Page 69 of 86 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11[19] G12[19] G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin H7 H8 H9 H10 H11[19] H12 [19] CY39050 NC IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 NC NC NC NC NC NC VCCIO0 IO/VREF0 NC IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG NC NC NC NC NC IO0 NC IO0 VCC VCCIO0 CY39100 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 NC NC NC IO/VREF0 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 NC NC NC IO0 IO0 IO0 VCC VCCIO0 CY39165 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 IO5 IO/VREF0 VCCIO0 IO/VREF0 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 VCCIO5 IO/VREF5 IO0 IO0 IO0 IO0 VCC VCCIO0 CY39200 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 IO5 IO/VREF0 VCCIO0 IO/VREF0 IO0 VCC VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 VCCIO5 IO/VREF5 IO0 IO0 IO0 IO0 VCC VCCIO0 Page 70 of 86 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 [19] CY39050 IO/VREF0 NC GCTL0 GND GND GND GND GCTL1 NC IO/VREF5 VCCIO5 NC NC NC NC NC GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 NC GCLK0 GND GND GND GND GCLK1 NC IO/VREF5 IO5 IO5 IO5 IO5 NC GND GND NC IO1 IO1 NC IO1 CY39100 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 NC GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND IO1 IO1 IO1 IO1 IO1 CY39165 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 IO5 GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND IO1 IO1 IO1 IO1 IO1 CY39200 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 IO5 GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND IO1 IO1 IO1 IO1 IO1 Page 71 of 86 L5[19] L6[19] L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17[19] L18[19] L19[19] L20 L21 L22 M1 M2 M3 M4 M5 M6[19] Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin M7[19] M8[19] M9 M10 M11 M12 M13 M14 M15[19] M16[19] M17[19] M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 CY39050 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 NC NC IO4 IO4 GND NC NC NC NC VCCPRG VCCIO1 IO/VREF1 NC NC GND GND GND GND NC IO4 IO/VREF4 VCCIO4 VCCPRG NC NC NC NC NC NC IO/VREF1 NC VCC VCCIO1 CY39100 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO4 IO4 GND NC IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 NC NC NC IO/VREF1 IO1 VCC VCCIO1 CY39165 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO4 IO4 GND IO1 IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 IO4 IO/VREF1 VCCIO1 IO/VREF1 IO1 VCC VCCIO1 CY39200 IO1 IO1 IO1 GND GND GND GND IO4 IO4 IO4 IO4 IO5 IO5 IO4 IO4 GND IO1 IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 IO4 IO/VREF1 VCCIO1 IO/VREF1 IO1 VCC VCCIO1 Page 72 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin P7 P8 P9 P10 P11[19] P12[19] P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11[19] R12[19] R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 CY39050 NC VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 NC IO/VREF4 VCCIO4 VCC NC NC NC NC NC NC IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 NC NC NC NC IO4 IO4 IO4 NC NC IO1 IO1 IO/VREF1 IO1 IO1 CY39100 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 NC NC NC IO1 IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 IO4 NC NC IO1 IO1 IO/VREF1 IO1 IO1 CY39165 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 VCCIO4 IO/VREF4 IO1 IO1 IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO1 IO1 IO1 IO/VREF1 IO1 IO1 CY39200 IO/VREF1 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 VCCIO4 IO/VREF4 IO1 IO1 IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 IO4 IO4 IO1 IO1 IO1 IO/VREF1 IO1 IO1 Page 73 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin T7 T8 T9 T10 T11[19] T12 [19] CY39050 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 NC NC IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO4 IO4 NC NC NC NC NC GND CCLK CY39100 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 NC NC IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO4 IO4 NC NC NC NC NC GND CCLK CY39165 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3[20] IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 IO4 IO1 IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3[20] IO3 GND IO4 IO4 IO4 IO4 IO4 IO1 IO1 IO1 IO1 GND CCLK CY39200 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 IO4 IO1 IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND IO4 IO4 IO4 IO4 IO4 IO1 IO1 IO1 IO1 GND CCLK Page 74 of 86 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 CY39050 IO2 NC VCCCNFG VCCIO2 IO2 IO2 NC VCCIO3 IO3 IO3 IO3 GND NC NC NC NC NC VCCIO1 NC GND Reset IO2 NC IO2 NC NC IO2 IO2 NC NC IO3 IO3 IO3 NC GND NC VCCIO4 NC NC NC NC IO2 IO2 IO2 CY39100 IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND NC NC NC NC NC VCCIO1 NC GND Reset IO2 IO2 IO2 IO/VREF2 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND NC VCCIO4 NC NC NC NC IO2 IO2 IO2 CY39165 IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 IO4 IO4 IO4 IO/VREF1 VCCIO1 IO1 GND Reset IO2 IO2 IO2 IO/VREF2 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND IO4 VCCIO4 IO/VREF4 IO2 IO2 IO2 IO2 IO2 IO2 CY39200 IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 IO4 IO4 IO4 IO/VREF1 VCCIO1 IO1 GND Reset IO2 IO2 IO2 IO/VREF2 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND IO4 VCCIO4 IO/VREF4 IO2 IO2 IO2 IO2 IO2 IO2 Page 75 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 CY39050 IO2 NC NC IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 NC NC NC NC NC GND GND NC VCCIO2 IO/VREF2 IO2 NC IO2 NC NC IO2 IO3 IO3 NC IO3 NC NC IO/VREF3 VCCIO3 NC GND GND GND GND NC CY39100 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 NC NC NC GND GND NC VCCIO2 IO/VREF2 IO2 IO2 IO2 NC IO2 IO2 IO3 IO3 NC IO3 IO3 IO3 IO/VREF3 VCCIO3 NC GND GND GND GND NC CY39165 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 NC NC NC GND GND IO2 VCCIO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 IO2 IO2 IO3 IO3 VCCIO3 IO3 IO3[20] IO3[20] IO/VREF3 VCCIO3 NC GND GND GND GND IO/VREF2 CY39200 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 GND GND IO2 VCCIO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 IO2 IO2 IO3 IO3 VCCIO3 IO3 IO3 IO3 IO/VREF3 VCCIO3 IO3 GND GND GND GND IO/VREF2 AB4 NC NC IO/VREF2 IO/VREF2 Note: 20. These I/Os have a slightly higher tPD (propagation delay) than the rest of the pins. The use of these pins on the same packages of different densities or the pins in the same relative position in smaller or larger FBGAs for signals with critical timing should be avoided. When first implementing a design in these packages, the timing-driven routing of Warp 6.2 and later versions will ensure these pins are avoided when routing critical signal. Document #: 38-03039 Rev. *H Page 76 of 86 Delta39KTM ISRTM CPLD Family Table 14. 484 FBGA Pin Table (continued) Pin AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 CY39050 IO2 IO2 IO2 NC NC NC GND GND IO3 IO3 IO3 NC IO3 NC NC NC GND GND CY39100 IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 NC NC GND GND CY39165 IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 NC NC GND GND Table 15. 676 FBGA Pin Table (continued) CY39200 GND NC IO7 IO7 IO7 VCCIO7 IO7 IO7 IO7 NC VCCIO7 NC GND GND NC VCCIO6 NC IO6 IO6 IO6 VCCIO6 IO6 IO6 Pin A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 Document #: 38-03039 Rev. *H CY39100 NC NC GND NC GND NC NC NC NC NC NC NC NC NC NC GND GND NC NC NC NC NC NC NC CY39165 NC NC GND NC GND IO7 IO7 IO7 NC IO7 IO7 IO7 IO7 IO7 IO7 GND GND NC NC NC NC NC NC NC CY39200 IO6 NC GND NC GND IO7 IO7 IO7 NC IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 Page 77 of 86 CY39200 IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 GND GND Table 15. 676 FBGA Pin Table Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CY39100 GND NC NC NC NC NC NC NC NC NC NC NC GND GND NC NC NC NC NC NC NC NC NC CY39165 GND NC IO7 IO7 IO7 VCCIO7 IO7 IO7 IO7 NC VCCIO7 NC GND GND NC VCCIO6 NC NC NC NC VCCIO6 NC NC Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 CY39100 NC NC NC GND NC NC NC GND GND NC NC IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 NC NC GND GND NC NC NC NC GND GND NC VCCIO7 IO7 IO7 IO7 IO/VREF7 NC IO7 IO7 CY39165 NC NC NC GND NC NC NC GND GND IO/VREF7 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 [20] Table 15. 676 FBGA Pin Table (continued) CY39200 IO6 IO6 NC GND NC NC NC GND GND IO/VREF7 IO/VREF7 IO7 IO7 IO7 IO7 IO7 IO7 GND GND IO6 IO6 IO6 IO6 IO6 IO6 IO/VREF6 IO6 GND GND NC NC NC NC GND GND IO7 VCCIO7 IO7 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 Pin D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 F3 F4 F5 CY39100 IO6 IO6 NC IO/VREF6 IO6 IO6 IO6 VCCIO6 NC GND GND NC NC NC NC NC NC NC IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 NC NC NC NC NC NC NC NC VCCIO0 NC CY39165 IO6 IO6 VCCIO6 IO/VREF6 IO6[20] IO6 IO6 VCCIO6 NC GND GND NC NC NC NC IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6 [20] CY39200 IO6 IO6 VCCIO6 IO/VREF6 IO6 IO6 IO6 VCCIO6 IO6 GND GND NC NC NC NC IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO7 IO/VREF7 IO7 IO6 IO/VREF6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 IO6 NC NC NC NC IO/VREF0 VCCIO0 IO0 Page 78 of 86 IO6[20] IO6 IO6 NC NC GND GND NC NC NC NC GND GND IO7 VCCIO7 IO7 IO7 IO7 IO/VREF7 VCCIO7 IO7 IO7 IO6[20] IO6 IO6 IO6 NC NC NC NC NC NC NC IO/VREF0 VCCIO0 IO0 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 CY39100 GND IO7 IO7 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND NC VCCIO5 NC NC NC NC NC NC NC NC IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO NC NC CY39165 GND IO7 IO7 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO5 VCCIO5 IO/VREF5 NC NC NC NC IO0 IO0 IO0 IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6[20] IO6 IO6 GND TDO IO5 IO5 CY39200 GND IO7 IO7 IO7 IO7 IO/VREF7 IO/VREF7 IO6/Lock IO6 IO/VREF6 IO/VREF6 IO6 IO6 IO6 IO6 GND IO5 VCCIO5 IO/VREF5 NC NC NC NC IO0 IO0 IO0 IO0 GND IO7 IO7 IO7 VCCIO7 VCC IO/VREF7 IO/VREF6 VCCPLL VCCIO6 IO6 IO6 IO6 GND TDO IO5 IO5 Table 15. 676 FBGA Pin Table (continued) Pin G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13[19] H14[19] H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 [19] CY39100 NC NC NC NC NC NC IO0 IO0 IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO5 IO5 NC NC NC NC NC NC IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 CY39165 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6[20] GND TDI IO5 IO5 IO5 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 CY39200 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 GND IO7 IO7 VCCIO7 VCCIO7 IO7 IO6 VCCIO6 VCCIO6 IO6 IO6 GND TDI IO5 IO5 IO5 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 IO0 GND IO7 IO/VREF7 IO7 IO7 IO6 IO6 Page 79 of 86 J14[19] J15 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13[19] K14[19] K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L7 CY39100 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 NC NC NC NC NC NC IO0 IO0 IO0 IO0 IO0 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 NC NC NC NC NC NC NC IO/VREF0 IO0 VCC CY39165 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 IO0 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6[20] TMS IO5 IO5 IO5 IO5 IO5 IO5 IO5 NC NC NC NC IO/VREF0 VCCIO0 IO/VREF0 IO0 VCC CY39200 IO/VREF6 IO6 GND TCLK IO5 IO5 IO5 IO5 IO5 NC NC NC NC IO0 IO0 IO0 IO0 IO0 IO0 IO0 IO7 IO7 IO7 IO7 IO6 IO6 IO6 TMS IO5 IO5 IO5 IO5 IO5 IO5 IO5 NC NC NC NC IO/VREF0 VCCIO0 IO/VREF0 IO0 VCC Table 15. 676 FBGA Pin Table (continued) Pin L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 CY39100 VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 NC NC NC NC NC NC NC IO0 IO0 IO0 VCC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 NC NC CY39165 VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 VCCIO5 IO/VREF5 NC NC NC NC IO0 IO0 IO0 IO0 VCC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 IO5 NC CY39200 VCCIO0 IO/VREF0 IO0 IO7 GCTL3 GCLK3 GCTL2 GCLK2 IO5 IO5 IO/VREF5 VCCIO5 VCCJTAG IO5 IO/VREF5 VCCIO5 IO/VREF5 NC NC NC NC IO0 IO0 IO0 IO0 VCC VCCIO0 IO/VREF0 IO0 GCTL0 GND GND GND GND GCTL1 IO5 IO/VREF5 VCCIO5 VCC IO5 IO5 IO5 IO5 NC Page 80 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin M26 N1 N2 N3 N4 N5 N6[19] N7[19] N8[19] N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19[19] N20[19] N21[19] N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P7 P8[19] P9 [19] Table 15. 676 FBGA Pin Table (continued) CY39200 NC GND GND GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND GND GND GND GND IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 Pin P18[19] P19[19] P20 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 CY39100 IO4 IO4 IO5 IO5 IO4 IO4 GND GND GND NC NC NC IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 NC NC NC NC NC NC NC IO/VREF1 IO1 VCC VCCIO1 IO/VREF1 CY39165 IO4 IO4 IO5 IO5 IO4 IO4 GND GND GND NC NC IO1 IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 IO4 NC NC NC NC IO/VREF1 VCCIO1 IO/VREF1 IO1 VCC VCCIO1 IO/VREF1 CY39200 IO4 IO4 IO5 IO5 IO4 IO4 GND GND GND NC NC IO1 IO1 IO1 IO1 VCCPRG VCCIO1 IO/VREF1 IO1 IO1 GND GND GND GND IO4 IO4 IO/VREF4 VCCIO4 VCCPRG IO4 IO4 IO4 IO4 NC NC NC NC IO/VREF1 VCCIO1 IO/VREF1 IO1 VCC VCCIO1 IO/VREF1 Page 81 of 86 CY39100 NC GND GND GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND GND GND GND GND IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 CY39165 NC GND GND GND IO0 IO0 IO0 IO0 IO0 IO/VREF0 IO0 GCLK0 GND GND GND GND GCLK1 IO5 IO/VREF5 IO5 IO5 IO5 IO5 IO5 GND GND GND GND GND GND IO1 IO1 IO1 IO1 IO1 IO1 IO1 IO1 GND GND GND GND IO4 IO4 P10[19] P11 P12 P13 P14 P15 P16 P17[19] Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin T10 T11 T12 T13 [19] Table 15. 676 FBGA Pin Table (continued) CY39200 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 VCCIO4 IO/VREF4 NC NC NC NC IO1 IO1 IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 IO4 IO4 NC NC NC Pin V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13[19] V14[19] V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 CY39100 NC NC IO1 IO1 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 NC NC NC NC NC NC IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND CY39165 NC IO1 IO1 IO1 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 IO4 NC NC NC NC IO1 IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND [20] CY39100 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 NC NC NC NC NC NC NC NC IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 NC NC NC NC NC CY39165 VCCCNFG Config_Done IO2 IO2 IO3 IO3 IO3 IO4 IO/VREF4 VCCIO4 VCC IO4 IO/VREF4 VCCIO4 IO/VREF4 NC NC NC NC IO1 IO1 IO1 IO1 IO1 IO1 Data Reconfig IO2 IO2 IO2 IO3 IO3 IO3 IO3 IO4 IO4 IO4 IO4 IO4 IO4 IO4 NC NC NC CY39200 NC IO1 IO1 IO1 IO/VREF1 IO1 IO1 GND MSEL IO/VREF2 IO/VREF2 IO2 IO3 IO/VREF3 IO/VREF3 IO3 GND IO4 IO4 IO/VREF4 IO4 IO4 IO4 NC NC NC NC IO1 IO1 IO1 IO1 IO1 GND CCE IO2 VCCIO2 VCCIO2 IO2 IO2 VCCIO3 VCCIO3 IO3 IO3 GND Page 82 of 86 T14[19] T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13[19] U14[19] U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 V1 IO/VREF3 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin W20 W21 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 CY39100 IO4 IO4 IO4 IO4 NC NC NC NC NC NC NC NC IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 NC NC NC NC NC NC NC NC VCCIO1 NC GND Reset IO2 IO2 IO2 IO/VREF2 CY39165 IO4 IO4 IO4 IO4 IO4 NC NC NC NC IO1 IO1 IO1 IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 IO4 IO4 IO4 NC NC NC NC IO/VREF1 VCCIO1 IO1 GND Reset IO2 IO2 IO2 IO/VREF2 CY39200 IO4 IO4 IO4 IO4 IO4 NC NC NC NC IO1 IO1 IO1 IO1 GND CCLK IO2 IO2 VCCCNFG VCCIO2 IO2 IO2 VCC VCCIO3 IO3 IO3 IO3 GND IO4 IO4 IO4 IO4 NC NC NC NC IO/VREF1 VCCIO1 IO1 GND Reset IO2 IO2 IO2 IO/VREF2 Table 15. 676 FBGA Pin Table (continued) Pin AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 CY39100 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND NC VCCIO4 NC NC NC NC NC NC NC NC IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 NC NC NC NC NC NC NC GND CY39165 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND IO4 VCCIO4 IO/VREF4 NC NC NC NC IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3[20] IO3 IO3 IO3 IO3 NC NC NC NC NC NC NC GND CY39200 IO/VREF2 IO2 IO2 IO/VREF3 IO/VREF3 IO3 IO3 IO3 IO3 GND IO4 VCCIO4 IO/VREF4 NC NC NC NC IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO2 IO/VREF2 IO2 IO3 IO/VREF3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 IO3 NC NC NC NC GND Page 83 of 86 Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 CY39100 GND NC VCCIO2 IO/VREF2 IO2 IO2 IO2 NC IO2 IO2 IO3 IO3 NC IO3 IO3 IO3 IO/VREF3 VCCIO3 NC GND GND NC NC NC NC GND GND NC NC IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 NC CY39165 GND IO2 VCCIO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 IO2 IO2 IO3 IO3 VCCIO3 IO3[20] IO3[20] IO3[20] IO/VREF3[20] VCCIO3 NC GND GND NC NC NC NC GND GND IO/VREF2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 [20] Table 15. 676 FBGA Pin Table (continued) CY39200 GND IO2 VCCIO2 IO/VREF2 IO2 IO2 IO2 VCCIO2 IO2 IO2 IO3 IO3 VCCIO3 IO3 IO3 IO3 IO/VREF3 VCCIO3 IO3 GND GND NC NC NC NC GND GND IO/VREF2 IO/VREF2 IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 NC NC NC NC NC NC GND GND NC NC NC NC NC NC NC NC NC NC GND NC GND NC NC NC NC NC NC NC NC NC NC NC IO2 IO2 IO2 IO2 IO2 IO2 GND GND NC NC NC NC NC NC NC NC NC NC GND NC GND NC IO2 IO2 IO2 VCCIO2 IO2 IO2 IO2 NC VCCIO2 NC IO2 IO2 IO2 IO2 IO2 IO2 GND GND IO3 IO3 IO3 IO3 IO3 IO3 IO/VREF3 IO3 IO3 NC GND NC GND NC IO2 IO2 IO2 VCCIO2 IO2 IO2 IO2 NC VCCIO2 NC Page 84 of 86 Pin AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 CY39100 NC GND GND NC NC NC GND NC NC NC NC CY39165 NC GND GND NC NC NC GND IO2 IO2 IO2 NC CY39200 IO3 GND GND NC NC NC GND IO2 IO2 IO2 NC IO3[20] IO3 IO3 NC Document #: 38-03039 Rev. *H Delta39KTM ISRTM CPLD Family Table 15. 676 FBGA Pin Table (continued) Pin AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 CY39100 GND GND NC NC NC NC NC NC NC NC NC NC NC GND CY39165 GND GND NC VCCIO3 NC NC NC NC VCCIO3 NC NC NC NC GND CY39200 GND GND NC VCCIO3 NC IO3 IO3 IO3 VCCIO3 IO3 IO3 IO3 NC GND Windows 95, Windows 98, Windows 2000, Windows XP, and Windows NT are trademarks of Microsoft Corporation. ZBT is a trademark of IDT. QDR is a trademark of Micron, IDT, and Cypress Semiconductor. Warp is a registered trademark, and NoBL, Programmable Interconnect Matrix, PIM, Spread Aware, AnyVolt, Self-Boot, In-System Reprogrammable, ISR, "CPLDs at FPGA Densities," True Vertical Migration, and Delta39K are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-03039 Rev. *H Page 85 of 86 (c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Delta39KTM ISRTM CPLD Family Document History Page Document Title: Delta39KTM ISRTM CPLD Family CPLDs at FPGA DensitiesTM Document Number: 38-03039 REV. ** *A ECN NO. 106503 107625 Issue Date 05/30/01 07/11/01 Orig. of Change SZV RN Description of Change Change from Spec #: 38-00830 to 38-03039 Deleted 39K15 device and the associated -250-MHz bin specs Deleted 144FBGA package and associated part numbers Changed ESD spec from "MIL-STD-883" to "JEDEC EIA/JESD22-A114-A" Changed the Prime bin for 39K50 and 39K30 from "MHz" to "233 MHz" Changed the part ordering information accordingly Updated the -233-MHz timing specs to match modified timing specs achieved by design (main affected params: tPD, tMCCO, tIOS, tSCS, tSCS2, fMAX2, tCLMAA, tCLMCYC2, tCHMCYC2, tCHMCLK) Updated I/O standard Timing Delay Specs and changed the default I/O standard from 3.3V PCI to LVCMOS Added paragraph about Delta39K being CompactPCI hot swap Ready Added X8 mode in the PLL description Added Standby ICC spec Updated the recommended boot PROM for 39K165/200 to be CY3LV002 instead of CY3LV020 Updated Delta39K family offering Modified PLL timing parameters tDWSA, tDWOSA, tMCCJ, and tLOCK. Added tINDUTY parameter Deleted exception to CompactPCI Hot Swap compliance regarding "PCI buffers...." Added reference to app note "Hot Socketing Delta39K" Revised CompactPCI Hot Swap Specification R1.0 to be R2.0 Combined with spec# 38-03040 Updated pin tables for 39K30 (208PQFP, 256FBGA) Updated pin tables for 39K50 (208PQFP, 256/484FBGA, 388BGA) Added X3, X5, X6, X16 multiplication modes to Spread Aware PLL Added PLL parameters (fPLLVCO, PSAPLLI, fMPPLI) Added and updated Storage Temperature for 39K200-208EQFP Changed the Icc0 spec for 39K165 and 39K200 Updated tCLZ, tCHMCYC2 parameter Values for -233 MHz bin Updated Input and Output Standard Timing Delay Adjustment table Removed Self Boot Industrial parts from the offering Removed Delta39K165Z (1.8V) from the offering Removed 144-FBGA package offering Added self-boot Flash Memory endurance and data retention data Added Family, Package, and Density Migration section Added note 20 to 484/676 FBGA pin table to identify slow 39K165 IOs Changed data sheet status from Preliminary to Final Added note 7 to DC Characteristics Updated spec 51-85103 (MG388 package drawing) to rev. *C Changed the definition of following pins on CY39030 -256FBGA package: Pin A10: From IO/Vref7 to IO/Vref6 Pin B7: From IO/Vref6 to VCC Added Table to identify Bank Location of Global Clock and Global Control Pins Removed all "Z" parts (1.8V) Referenced EEPROM to ATMEL part number *B 109681 11/16/01 RN *C *D 112376 112946 12/21/01 04/04/02 RN RN *E *F *G 117518 121063 122543 10/04/02 11/06/02 12/10/02 OOR DSG RN *H 128684 08/04/03 OOR Document #: 38-03039 Rev. *H Page 86 of 86